Henry Cook
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837d207064
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[travis] split up groundtest into two suites
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2016-11-23 12:27:40 -08:00 |
|
Henry Cook
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38c5af5bad
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[rocket] cleanup mshr logic
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2016-11-23 12:09:56 -08:00 |
|
Henry Cook
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dae6772624
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factor out common cache subcomponents into uncore.util
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2016-11-23 12:09:35 -08:00 |
|
Henry Cook
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16d0f522b0
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[tracegen] filter seed report
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2016-11-23 12:09:09 -08:00 |
|
Henry Cook
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c65c255815
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[coreplex] TileId moved to groundtest
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2016-11-23 12:08:45 -08:00 |
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Wesley W. Terpstra
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cf8ecbd53b
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travis: balance regression tasks a bit more fairly
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2016-11-23 10:28:22 -08:00 |
|
Wesley W. Terpstra
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e8e95d4bcf
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regression: remove cde submodule update
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2016-11-23 10:28:22 -08:00 |
|
Wesley W. Terpstra
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a93d34742a
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rocketchip: bump all submodules (and remove cde)
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2016-11-23 10:28:22 -08:00 |
|
Wesley W. Terpstra
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612f96b2af
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Merge pull request #447 from ucb-bar/axi4-master
Axi4 master
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2016-11-23 10:23:43 -08:00 |
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Wesley W. Terpstra
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1d3cad3671
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tilelink2 SourceShrinker: handle degenerate cases for free
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2016-11-22 22:17:30 -08:00 |
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Wesley W. Terpstra
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1e7d597fd3
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rocketchip: don't waste too many sources on the AXI master port
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2016-11-22 21:48:41 -08:00 |
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Wesley W. Terpstra
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c0b27999ea
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tilelink2 SourceShrinker: a concurrency reducing adapter
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2016-11-22 21:43:38 -08:00 |
|
Wesley W. Terpstra
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0097274ea3
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Broadcast: single-cycle response is possible
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2016-11-22 20:45:40 -08:00 |
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Wesley W. Terpstra
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437be0f36a
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PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool))
This results in much less Verilog to simulate
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2016-11-22 20:39:38 -08:00 |
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Wesley W. Terpstra
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f9de7173cc
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PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...))
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2016-11-22 18:46:11 -08:00 |
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Wesley W. Terpstra
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d9a203b0f0
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PositionalMultiQueue: convert 'next' to a single write port
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2016-11-22 18:38:55 -08:00 |
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Wesley W. Terpstra
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13190a5de0
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rocketchip: re-add AXI4 interface
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2016-11-22 17:27:58 -08:00 |
|
Wesley W. Terpstra
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c230580157
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coreplex: rename RocketPlex => RocketTiles
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2016-11-22 17:27:58 -08:00 |
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Wesley W. Terpstra
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bbabcf67ff
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coreplex: width adapter should happen as part of coherence manager
In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
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2016-11-22 17:27:58 -08:00 |
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Wesley W. Terpstra
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a140b07009
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rocketchip: cut coreplex from rocketchip
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2016-11-22 17:27:58 -08:00 |
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Wesley W. Terpstra
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c80ee06472
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rocketchip: configString is a lazy property of outer
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2016-11-22 17:27:58 -08:00 |
|
Andrew Waterman
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5f3fb64ef0
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Per ABI, only x1 and x5 should be treated as function returns
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
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2016-11-22 12:01:05 -08:00 |
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Yunsup Lee
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42b40130e2
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Merge pull request #443 from ucb-bar/tl2-tlb
Tl2 tlb
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2016-11-21 22:00:30 -08:00 |
|
Wesley W. Terpstra
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3d644b943c
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coreplex: configString is a property of the RISCVPlatform
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2016-11-21 21:13:26 -08:00 |
|
Wesley W. Terpstra
|
e8be365b5d
|
rocketchip: remove GlobalAddrMap completely
|
2016-11-21 21:13:26 -08:00 |
|
Wesley W. Terpstra
|
5fe107bb07
|
rocket: pass scratchpad address to block dcache
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2016-11-21 21:13:26 -08:00 |
|
Wesley W. Terpstra
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c18bc07bbc
|
TLB: determine RWX from TL2 properties directly
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2016-11-21 21:13:26 -08:00 |
|
Wesley W. Terpstra
|
3d1a7bd6d3
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travis: build verilator and toolchain as part of install
|
2016-11-21 21:13:26 -08:00 |
|
Wesley W. Terpstra
|
ea3ec89676
|
travis: split RocketSuite into three smaller tests suites
|
2016-11-21 21:13:23 -08:00 |
|
Wesley W. Terpstra
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1577deb324
|
travis: delete oldest caches; not newest
|
2016-11-21 21:10:29 -08:00 |
|
Henry Cook
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94cc1efadc
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Merge pull request #440 from ucb-bar/tl2-tile
TL2 take-over of the L1
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2016-11-20 20:44:59 -08:00 |
|
Henry Cook
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28c6be90ab
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[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
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2016-11-20 19:36:51 -08:00 |
|
Henry Cook
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ff9b5bf8fc
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[rocket] nbdcache release bugfix
|
2016-11-20 19:07:06 -08:00 |
|
Henry Cook
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e68795421a
|
remove L2 regressions for now
|
2016-11-19 20:11:20 -08:00 |
|
Henry Cook
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3f47d5b5eb
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[rocket] re-enable working NBDcache (passes Tracegen)
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2016-11-19 19:19:16 -08:00 |
|
Henry Cook
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c31b41a7ac
|
[tl2] add grant finisher comment
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2016-11-19 19:16:43 -08:00 |
|
Colin Schmidt
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9dd12545d0
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[Rocket] Send correct type for iomshr reqs
Also contain grow param bugfix
|
2016-11-19 19:04:06 -08:00 |
|
Wesley W. Terpstra
|
32a1c27441
|
rocket: disable nbdcache until it's fully ported
|
2016-11-18 19:55:24 -08:00 |
|
Wesley W. Terpstra
|
452bb2fc80
|
dcache fix TinyConfig
|
2016-11-18 19:50:34 -08:00 |
|
Wesley W. Terpstra
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d1328a6b6f
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rocketchip: remove most uses of GlobalAddrMap
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2016-11-18 19:38:02 -08:00 |
|
Henry Cook
|
2976fd84e4
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[rocket] resolve cde/config conflicts
|
2016-11-18 19:11:34 -08:00 |
|
Henry Cook
|
8b908465e0
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[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
|
2016-11-18 19:04:06 -08:00 |
|
Henry Cook
|
5f1cc19d71
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[tl2] fix comment explaining permissions
|
2016-11-18 19:02:17 -08:00 |
|
Henry Cook
|
10112da4e7
|
[tl2] won't need putthrough opcode
|
2016-11-18 19:02:17 -08:00 |
|
Wesley W. Terpstra
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001d9821bd
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Merge remote-tracking branch 'origin/master' into tl2-tile
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2016-11-18 18:19:41 -08:00 |
|
Wesley W. Terpstra
|
5b594ced29
|
Plic: support 0 interrupts gracefully
|
2016-11-18 18:07:44 -08:00 |
|
Wesley W. Terpstra
|
13ec3853ed
|
junctions: get unit tests running again
|
2016-11-18 17:38:46 -08:00 |
|
Wesley W. Terpstra
|
10dd6070ad
|
groundtest: gracefully handle zero uncached ports
|
2016-11-18 17:26:28 -08:00 |
|
Wesley W. Terpstra
|
03bca77b33
|
tilelink2 Metadata: cannot assert data good when !valid
|
2016-11-18 17:16:12 -08:00 |
|
Wesley W. Terpstra
|
be8121eeaf
|
coreplex: fix clock crossing
|
2016-11-18 17:15:57 -08:00 |
|