b566ffedea
system: fix DefaultFPGAConfig ( #1047 )
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It was missing cores. Fixes #736 .
2017-10-11 10:48:41 -07:00
8e1a002c4e
Merge pull request #1033 from freechipsproject/dont-touch
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Use chisel3.experimental.dontTouch (take 2)
2017-10-11 00:59:37 -07:00
329a5c35d4
tilelink: unsafe cache cork discards outer d.sink
2017-10-11 00:30:51 -07:00
1240cb275c
coreplex: TilePortParams formatting
2017-10-11 00:29:11 -07:00
6f3a4cd733
build: pass annotations to firrtl
2017-10-10 23:42:55 -07:00
5d62c321f4
generator: create annotation file
2017-10-10 23:23:06 -07:00
75345b6048
rocket: don't remove ports on top module
2017-10-10 21:28:59 -07:00
5ff4c1674a
Merge pull request #1044 from freechipsproject/nicer-clint
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clint: use RegField.toBytes to save some work
2017-10-10 20:33:00 -07:00
b3bdf5eca6
RegField: default argument for .bytes
2017-10-10 19:49:35 -07:00
e094b94ce5
clint: use RegField.toBytes to save some work
2017-10-10 19:49:35 -07:00
10472b4296
diplomacy: auto connect bundles in a stable order ( #1045 )
2017-10-10 19:41:46 -07:00
1867a5b226
rocket: only cache when AcquireT is possible
2017-10-10 18:06:58 -07:00
b2bc46471b
Conditionalize some covers that are sometimes impossible ( #1043 )
2017-10-10 17:14:33 -07:00
ef28ce8d2f
Merge pull request #1042 from freechipsproject/bump-riscv-tools
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Bump riscv-tools.
2017-10-10 16:31:38 -07:00
37406706b4
coreplex: move CacheCork in front of SBus
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Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
2017-10-10 16:24:32 -07:00
8f5f80f958
coreplex: TileSlavePortParams inject adapters into PBus
2017-10-10 15:25:08 -07:00
660355004e
coreplex: TileMasterPortParams inject adapters into SBus
2017-10-10 15:02:50 -07:00
167aa7b793
Bump riscv-tools.
2017-10-10 14:14:10 -07:00
50429daef4
Merge pull request #1036 from freechipsproject/l1-cover
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Add some covers for L1 memory system
2017-10-10 12:28:48 -07:00
9026646459
coreplex: first cut at using RocketCrossingParams
2017-10-10 12:02:04 -07:00
d6766a8c68
RocketTile: make sure 'hartid' is available for traits ( #1037 )
2017-10-09 21:03:18 -07:00
a9686ab883
Merge pull request #1035 from freechipsproject/big-paddr
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Fix paddrBits < xLen && paddrBits == vaddrBits case
2017-10-09 20:59:21 -07:00
1474ab438d
Remove extraneous signal
2017-10-09 18:33:50 -07:00
f3825270c1
Add some covers for L1 memory system
2017-10-09 18:33:36 -07:00
2c4009a138
Fix paddrBits < xLen && paddrBits == vaddrBits case
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Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
2017-10-09 16:48:04 -07:00
0e6aa7ae9d
Merge pull request #1024 from freechipsproject/jtag_coverage
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Add Coverage points for JTAG TAP
2017-10-09 12:29:18 -07:00
d78ad857ee
Merge pull request #1034 from freechipsproject/base-tile
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Generalize Tile/Coreplex hierarchy
2017-10-09 11:42:20 -07:00
0916cf1bdd
JTAG Coverage: Correct jtag_reset case
2017-10-09 09:54:15 -07:00
9efe1c448e
Merge remote-tracking branch 'origin/master' into HEAD
2017-10-09 09:48:38 -07:00
986cbfb6b1
For Rockets without VM, widen vaddrBits to paddrBits
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This supports addressing a >39-bit physical address space.
2017-10-08 01:21:47 -07:00
a0e5a20b60
Don't route branch comparison result through ALU output mux
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This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
2017-10-07 17:36:24 -07:00
36c39d01e4
Factor out most of HasRocketTiles into HasTiles
2017-10-07 17:36:24 -07:00
70a4127cb8
Factor out some of HaveRocketTiles into HaveTiles
2017-10-07 17:36:24 -07:00
34e96c03b1
Move HCF to BaseTile
2017-10-07 17:36:24 -07:00
71205b70cc
Make RocketTileWrapper a BaseTile
2017-10-07 17:36:24 -07:00
4645b61fd3
Decouple BaseTile from HasTileLinkMasterPort
2017-10-07 17:36:24 -07:00
86a1953287
Merge pull request #1032 from freechipsproject/fpga_pipeline_fpu_master
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FPU FMA FPGA retiming assist
2017-10-05 20:11:34 -07:00
5498468743
FPU : simplify pipeline register generation in FMA
2017-10-05 15:18:19 -07:00
7a46715cbc
FPU : to assist retiming move upto first 2 register stages of into FMA
2017-10-05 15:18:04 -07:00
bd045a3b95
tilelink: split Acquire into Acquire{Block,Perm} ( #1030 )
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We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.
Instead of calling it Overwrite, we decided to split the Acquire type.
If you AcquirePerm, you MUST Release and ProbeAck with Data.
2017-10-05 12:49:49 -07:00
81b9ac42a3
add comments to diplomacy resource. ( #913 )
2017-10-05 12:45:56 -07:00
9040d921b5
Merge pull request #1031 from freechipsproject/non-contiguous-hartids
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Miscellaneous multicore cleanup
2017-10-05 12:44:31 -07:00
8da7aabd51
tile: supply hartid from RocketTileParams
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make WithNCores partial configs override rather than append more tiles
2017-10-05 00:31:53 -07:00
45581e60f0
Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"
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This reverts commit 5232a29d7da2dc13669a
2017-10-05 00:26:44 -07:00
5a84564203
Merge pull request #1023 from freechipsproject/csr-cleanup
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Generalize CSR file to support simpler cores
2017-10-04 14:04:59 -07:00
32fda51a2c
Get rid of paddrBits from SystemBus ( #1029 )
2017-10-04 12:11:37 -07:00
7bcf28c585
Define fetchBytes in HasCoreParams, not Frontend
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It is more generally useful.
2017-10-03 17:34:18 -07:00
2786e42d99
Don't register interrupts in CSRFile
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They are usually registered outside the tile in a CDC.
2017-10-03 17:34:18 -07:00
5cfe070932
Add option to make misa read-only
2017-10-03 17:34:18 -07:00
09468a272b
Add option to remove basic counters (mcycle/minstret)
2017-10-03 17:34:18 -07:00
Wesley W. Terpstra
Henry Cook
Andrew Waterman
Richard Xia
Richard Xia
Andrew Waterman
Megan Wachs
Henry Styles
Wei Song (宋威)