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Author SHA1 Message Date
Wesley W. Terpstra b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra e2ec1d00ad copyright: normalize /// to // in comments 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra 233280e7d2 AsyncBundle: save a wasted bit when depth=1 2016-11-25 18:11:01 -08:00
Wesley W. Terpstra 9f1c668c4f config: when modifying Parameters, subordinate lookups use top 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra 437be0f36a PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool)) 
This results in much less Verilog to simulate
 2016-11-22 20:39:38 -08:00
Wesley W. Terpstra f9de7173cc PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...)) 2016-11-22 18:46:11 -08:00
Wesley W. Terpstra d9a203b0f0 PositionalMultiQueue: convert 'next' to a single write port 2016-11-22 18:38:55 -08:00
Wesley W. Terpstra 37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 40daea2e15 util: Config scheme supporting up with ++ 2016-11-18 16:18:30 -08:00
Wesley W. Terpstra e5febcfa33 rocketchip: there are no more useful parameters to dump 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra 30425d1665 rocketchip: eliminate all Knobs 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra 119ccae9af rocketchip: don't use explicit cde namespace 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra 10e459fedb rocket: change connection between rocketchip and coreplex 
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
 2016-11-15 18:27:52 -08:00
Henry Cook afa1a6d549 WIP uncore and rocket changes compile 2016-11-10 15:57:29 -08:00
Jacob Chang fc5eb7cc64 Fixed AsyncFifo with reset messaging 2016-10-25 16:45:08 -07:00
Wesley W. Terpstra ac0bb841da AsyncQueue: cope with far reset propagation delay 2016-10-14 18:05:35 -07:00
Wesley W. Terpstra 1b09f1360d AsyncQueue: adjust register names to match vals 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra e7f8a7e9ea AsyncQueue: make it clear that the SyncChain is not Gray specific 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra 52b8121e68 Apply "async_queue: Give names to all the registers which show up in the queue (#390)" 
Adjusted to include names for the new registers.
Changes to RegisterCrossing were discarded.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra ffb734ac0e AsyncQueue: disambiguiate the reset_n signal names 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 5ee53c61d6 util: clarify an AsyncQueue corner-case 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 609fd97a71 util: AsyncQueue detect power-down/reset of non-empty queue 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 75bb94017b util: resynchronize AsyncQueue counters when far side resets 
If the other clock domain is much faster than ours, it's reset
might be shorter than a single cycle in our domain. In that case,
we need to catch the reset and extend it.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 5e2609bdd2 AsyncQueueSource: don't feed reset into normal logic! 
There is no need to block writes to mem during reset.
The Queue must be empty anyway.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 2f6985efd3 crossings: use flip not flip() 
This seems to be the more common API
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra cb7b16f1a9 util: exchange resets between AsyncQueue source and sink 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 8c7d469a95 Revert "async_queue: Give names to all the registers which show up in the queue (#390)" 
This reverts commit a84a961a39.

The changes to RegisterCrossing.scala were unneeded after application of this branch.
The name changes made to the AsyncQueue.scala are reapplied at the end of this branch.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra dcb9383568 PositionalMultiQueue: work around vcs Lint report 
Lint-[PCTIO-L] Ports coerced to inout
rocket-chip/vsim/generated-src/unittest.UncoreUnitTestConfig.v, 127524
"io_deq_0_valid"
  Port "io_deq_0_valid" declared as output in module "PositionalMultiQueue_16"
  may need to be inout. Coercing to inout.
 2016-10-10 11:21:49 -07:00
Wesley W. Terpstra 5d905a5310 PositionalMultiQueue: shared storage FIFO 1-push n-pop 2016-10-10 11:21:49 -07:00
Andrew Waterman 7f429e8799 Simplify AsyncResetReg 
No need for AsyncSetReg, as AsyncResetReg can be used exclusively with
inverted inputs.
 2016-10-08 21:29:40 -07:00
mwachs5 a84a961a39 async_queue: Give names to all the registers which show up in the queue (#390) 
This is to aid debugging but even more so for backend constraint writers, who generally
need predictable names for registers to set false paths, etc.
 2016-10-08 17:50:50 -07:00
Andrew Waterman 4fd03ffdf1 Fix PopCountAtLeast, un-breaking BTB 2016-10-07 21:20:40 -07:00
Andrew Waterman 5980dc160f Don't allow multiple entries for same PC in BTB 
Necessary for RVC forward-progress guarantee.
 2016-10-06 11:30:45 -07:00
mwachs5 e952f8f222 asyncqueue: Fix typo in the Async Queue (#381) 
* asyncqueue: Fix typo in the Async Queue that would cause the sync depth to be one less than expected.

* asyncqueue: Typo in the typo fix
 2016-10-04 21:02:06 -07:00
Yunsup Lee 62954d543e correctly initialize the active flag 2016-10-03 17:56:30 -07:00
Wesley W. Terpstra f05298d9bc tilelink2: move general-purpose code out of tilelink2 package 2016-10-03 16:22:28 -07:00
Wesley W. Terpstra 0a4ef66894 BaseTop: record top module; more general than GraphML 2016-10-03 15:05:45 -07:00
mwachs5 9a381e88d1 Suggest sane names for common objects (#369) 
* Suggest sane names for common objects frequently instantiated with factory methods

* Suggest names for common primitives using more Scala-esque Options
 2016-09-30 16:19:25 -07:00
Wesley W. Terpstra 20f42a8762 tilelink2: reuse the halves of the AsyncQueue 2016-09-29 17:35:08 -07:00
Howard Mao ab3219cf6e don't use Scala to Chisel implicit conversions outside of rocket 2016-09-29 14:35:42 -07:00
Howard Mao 9910c69c67 Move a bunch more things into util package 
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
 2016-09-29 14:23:42 -07:00
Wesley W. Terpstra dd9558f45d rocketchip: generate GraphML output 2016-09-26 14:35:46 -07:00
Henry Cook 1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config 2016-09-22 16:03:51 -07:00
Henry Cook 411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
Henry Cook 47c5d1a992 [WIP] Move RocketTestSuite generation into RocketchipGenerator 2016-09-22 14:31:45 -07:00
Howard Mao cd96a66ba6 replace verilog clock divider with one written in Chisel 2016-09-22 11:32:29 -07:00
Henry Cook 335e866176 [unittest] Parallelize UnitTestSuite (#319) 
* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.

* [util] Timer spacing cleanup

* [unittest] Remove Config reference to UnitTestTimeout
 2016-09-21 13:05:22 -07:00
Henry Cook 245f8ab76b [util] move LatencyPipe into util 2016-09-15 13:30:34 -07:00
Henry Cook be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
Howard Mao bdb7b1de36 move tilelink-agnostic counters from uncore to util package 2016-09-13 20:47:05 -07:00
Howard Mao 1882241493 move junctions utils into top-level utils package 2016-09-13 20:47:04 -07:00
Henry Cook 7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00