| .. |
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Arbiters.scala
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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AsyncBundle.scala
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AsyncBundle: save a wasted bit when depth=1
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2016-11-25 18:11:01 -08:00 |
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AsyncQueue.scala
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Fixed AsyncFifo with reset messaging
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2016-10-25 16:45:08 -07:00 |
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BlackBoxRegs.scala
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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ClockDivider.scala
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replace verilog clock divider with one written in Chisel
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2016-09-22 11:32:29 -07:00 |
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Config.scala
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config: when modifying Parameters, subordinate lookups use top
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2016-11-23 20:44:45 -08:00 |
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ConfigUtils.scala
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make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs
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2016-09-15 13:04:01 -07:00 |
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Counters.scala
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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Crossing.scala
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crossings: use flip not flip()
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2016-10-10 13:13:31 -07:00 |
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GeneratorUtils.scala
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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GenericParameterizedBundle.scala
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tilelink2: move general-purpose code out of tilelink2 package
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2016-10-03 16:22:28 -07:00 |
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HellaQueue.scala
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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LatencyPipe.scala
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[util] move LatencyPipe into util
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2016-09-15 13:30:34 -07:00 |
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Misc.scala
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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Package.scala
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Fix PopCountAtLeast, un-breaking BTB
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2016-10-07 21:20:40 -07:00 |
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PositionalMultiQueue.scala
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PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool))
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2016-11-22 20:39:38 -08:00 |
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ReorderQueue.scala
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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Timer.scala
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correctly initialize the active flag
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2016-10-03 17:56:30 -07:00 |
