Wesley W. Terpstra 233280e7d2 AsyncBundle: save a wasted bit when depth=1

2016-11-25 18:11:01 -08:00

..

Arbiters.scala

rocketchip: move from using cde to config

2016-11-18 16:18:33 -08:00

AsyncBundle.scala

AsyncBundle: save a wasted bit when depth=1

2016-11-25 18:11:01 -08:00

AsyncQueue.scala

Fixed AsyncFifo with reset messaging

2016-10-25 16:45:08 -07:00

BlackBoxRegs.scala

rocketchip: move from using cde to config

2016-11-18 16:18:33 -08:00

ClockDivider.scala

replace verilog clock divider with one written in Chisel

2016-09-22 11:32:29 -07:00

Config.scala

config: when modifying Parameters, subordinate lookups use top

2016-11-23 20:44:45 -08:00

ConfigUtils.scala

make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs

2016-09-15 13:04:01 -07:00

Counters.scala

rocketchip: move from using cde to config

2016-11-18 16:18:33 -08:00

Crossing.scala

crossings: use flip not flip()

2016-10-10 13:13:31 -07:00

GeneratorUtils.scala

rocketchip: move from using cde to config

2016-11-18 16:18:33 -08:00

GenericParameterizedBundle.scala

tilelink2: move general-purpose code out of tilelink2 package

2016-10-03 16:22:28 -07:00

HellaQueue.scala

rocketchip: move from using cde to config

2016-11-18 16:18:33 -08:00

LatencyPipe.scala

[util] move LatencyPipe into util

2016-09-15 13:30:34 -07:00

Misc.scala

rocketchip: move from using cde to config

2016-11-18 16:18:33 -08:00

Package.scala

Fix PopCountAtLeast, un-breaking BTB

2016-10-07 21:20:40 -07:00

PositionalMultiQueue.scala

PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool))

2016-11-22 20:39:38 -08:00

ReorderQueue.scala

rocketchip: move from using cde to config

2016-11-18 16:18:33 -08:00

Timer.scala

correctly initialize the active flag

2016-10-03 17:56:30 -07:00