Howard Mao
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38e0967816
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strip DMA and RoCC CSRs out of rocket and uncore (#201)
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2016-08-15 23:08:55 -07:00 |
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Andrew Waterman
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458520c8f6
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Use a generic UInt for TileLink op sizes, rather than MT_xx enum
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2016-08-09 15:24:51 -07:00 |
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Howard Mao
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0a85e92652
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Allow additional internal MMIO devices to be created without changing BaseConfig
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2016-08-04 11:04:52 -07:00 |
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Andrew Waterman
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791a27748b
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Update firrtl and remove firrtl hack in plic
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2016-08-02 15:19:48 -07:00 |
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Andrew Waterman
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832e56d3c7
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Fix toBits/toUInt/toSInt deprecation warnings
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2016-07-31 17:13:52 -07:00 |
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Wesley W. Terpstra
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11ec5b2cf4
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bram: don't deal with multibeat; rely on the fragmenter
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2016-07-22 14:51:05 -07:00 |
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Wesley W. Terpstra
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fa8317fec1
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debug: add clock crossing primitives
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2016-07-19 14:52:43 -07:00 |
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Howard Mao
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84098db81f
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add a TileLinkTestRAM
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2016-07-15 11:03:26 -07:00 |
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Albert Ou
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4c07aedfad
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Rewrite BRAMSlave to infer a single BRAM instance
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2016-07-05 14:21:21 -07:00 |
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Howard Mao
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9feca99d5d
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make PutBlock wmask argument match Put
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2016-06-28 13:10:46 -07:00 |
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Howard Mao
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b936aa9826
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refactor uncore files into separate packages
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2016-06-28 13:10:46 -07:00 |
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