Henry Cook
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4fbb0f80ff
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Added some multicore/multibanks named ChiselConfigs
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2015-07-06 18:21:06 -07:00 |
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Henry Cook
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d3ccec1044
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Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
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2015-07-02 14:43:30 -07:00 |
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Yunsup Lee
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702ddabe26
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add ExampleSmallConfig for README
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2014-10-07 02:07:59 -07:00 |
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Yunsup Lee
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e25d420155
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Improve ChiselConfig composability; bump chisel
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2014-10-06 13:43:40 -07:00 |
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Yunsup Lee
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73eac94a65
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Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
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2014-10-06 13:40:35 -07:00 |
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Henry Cook
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0b5f23a209
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Streamlined uncore for release
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2014-10-06 13:37:15 -07:00 |
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Adam Izraelevitz
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15fb4730ec
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Add BuildTile parameter for Tile
Conflicts:
rocket
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2014-09-25 06:50:45 -07:00 |
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Henry Cook
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7398b00d93
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dir supplied by function
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2014-09-25 06:50:41 -07:00 |
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Henry Cook
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5a840c5520
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support for multiple tilelink paramerterizations in same design
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2014-09-25 06:50:30 -07:00 |
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Scott Beamer
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f2ca887de3
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better fpga configs
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2014-09-25 06:47:03 -07:00 |
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Scott Beamer
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f4e6cd75ab
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turn off fpu for default fpga config.
a larger fpga can use defaultconfig
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2014-09-25 06:46:16 -07:00 |
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Yunsup Lee
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09de2e2794
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compute number of outstanding misses for DRAMSideLLCNull
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2014-09-12 18:09:38 -07:00 |
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Yunsup Lee
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1cfd9f5a0e
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add LICENSE
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2014-09-12 10:15:04 -07:00 |
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Yunsup Lee
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c98afa1fea
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turn off DRAMSideLLC
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2014-09-11 22:10:25 -07:00 |
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Yunsup Lee
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b5a64487eb
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turn off DRAMSideLLC
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2014-09-11 22:07:44 -07:00 |
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Yunsup Lee
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02c08a156f
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generate consts.vh from chisel source
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2014-09-10 17:14:55 -07:00 |
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Yunsup Lee
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ddfd3ce968
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further generalize fpga/vlsi builds
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2014-09-08 00:21:57 -07:00 |
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Henry Cook
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ae05125f29
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Adjustements to top-level parameters and knobs for hwacha
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2014-09-07 17:57:33 -07:00 |
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Henry Cook
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4126678c9d
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Merge branch 'dse'
Conflicts:
rocket
uncore
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2014-09-06 06:59:14 -07:00 |
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Henry Cook
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82467313dd
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merge in rocketchip changes from master
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2014-09-02 13:51:57 -07:00 |
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Henry Cook
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78ab83d224
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refactor fpga top/config
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2014-08-28 13:07:54 -07:00 |
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Henry Cook
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bf356b9cb4
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Refactor to combine fpga and vlsi tops, part 1
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2014-08-24 19:30:53 -07:00 |
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Henry Cook
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a41d55b643
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Final parameter refactor.
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2014-08-23 01:26:03 -07:00 |
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