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riscv/rocket-chip
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577 Revīzijas 1 Atzars 0 Tagi
4dad5b8b32dac06601cfff1d048eadcc30a8873b
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11 Revīzijas
Autors SHA1 Ziņojums Datums
Palmer Dabbelt 00465b15c3 Allow the regression Makefile to clean all targets 2016-01-31 23:06:59 -08:00
Henry Cook d21ffa4dba Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 00:24:07 -07:00
Yunsup Lee a99b1e3a01 append config name to generated Makefrag filename 2015-07-17 12:34:49 -07:00
Yunsup Lee e7802825c3 add Zscale testing 2015-07-17 12:02:02 -07:00
Yunsup Lee d6df479870 move 'include /Makefrag' out of top-level Makefrag 2015-07-14 16:13:32 -07:00
Yunsup Lee 221007595b allow BACKEND/CONFIG be environment variables 2014-09-17 11:12:08 -07:00
Yunsup Lee 275b72368b add CONFIG to the name of simulator executable 2014-09-11 22:11:58 -07:00
Yunsup Lee ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Yunsup Lee 763c57931b fix problem introduced with verilog generation in vsim/fsim 2014-09-04 09:49:57 -07:00
Scott Beamer 6c6f5a3843 add verilog target to build without simulator 2014-09-03 17:28:45 -07:00
Yunsup Lee c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
Darbina Gitea Versija: 1.27.3 Lapa: 23ms Sagatave: 4ms
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