Rimas Avizienis
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4bd0263a4a
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added misaligned instruction check, cleaned up badvaddr handling
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2011-11-10 03:38:59 -08:00 |
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Rimas Avizienis
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603ede8bfe
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access faults now write badvaddr PCR register with faulting address
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2011-11-10 02:46:09 -08:00 |
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Rimas Avizienis
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36aa4bcc9d
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moved exception handling from ex stage in dpath to mem stage in ctrl
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2011-11-10 02:26:26 -08:00 |
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Rimas Avizienis
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c29d2821b4
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cleanup, fixes, initial commit for dtlb.scala
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2011-11-09 21:54:11 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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