4b86802b1a
change the configuration interface of SlowIO
2016-09-29 22:16:53 -07:00
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
c45cc76cef
Get rid of remaining MemIO code
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The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
2016-09-27 16:28:17 -07:00
c77c244016
Get rid of NASTI memory interconnects
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These were made for a previous Hurricane tapeout, but we are now doing
all of the memory routing in TileLink, so they are no longer needed.
2016-09-27 16:28:17 -07:00
14cd39e045
rocketchip: rename identically names devices with _%d ( #340 )
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* rocketchip: rename identically names devices with _%d
If you connect two devices with the same name in TL2 (totally ok there),
when they get put into the TL1 addrmap, one gets silently overwritten.
This renames the second occurance as _1, third as _2, and so on...
* junctions: blow if duplicates add to addrmap
2016-09-26 13:05:49 -07:00
8641639873
Async rst async queue ( #336 )
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* crossing: use async reset
* crossings: asyncqueue needs Asynchronous reset.
* crossing: Actually enable the head of the synchronizer flop chain
* crossing: remove reset from logic. This flop will no longer be written during reset because valid will be low.
* crossing: Tidy up code & comments
2016-09-26 11:08:38 -07:00
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
8e63f4a1a5
Remove ClockToSignal and vice-versa
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Clock.asUInt and Bool.asClock now suffice.
2016-09-21 16:17:14 -07:00
1b26d78114
correctly print out the addrmap overlapping error message
2016-09-19 13:34:58 -07:00
fb24e847fd
rocketchip: globals are for sissies
2016-09-15 21:28:56 -07:00
0a65238920
Merge branch 'master' into tl2-irrevocable
2016-09-15 10:30:50 -07:00
646527c88e
use named constants to set AXI resp, cache, and prot fields
2016-09-14 21:16:54 -07:00
cde104b3fa
[junctions] Removes the obsoleted SMI.
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Closes #280 .
2016-09-14 20:06:22 -07:00
d35060b881
[junctions] messed up the merge lulz
2016-09-14 17:55:16 -07:00
1b53e477fa
Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
2016-09-14 17:50:17 -07:00
08c4c7b985
[junctions] make async crossings capable of providing IrrevocableIO
2016-09-14 17:38:54 -07:00
1308680f75
Add some async/clock utilities
2016-09-14 16:30:59 -07:00
5828e6042e
Work around https://github.com/ucb-bar/firrtl/issues/299
2016-09-14 11:47:10 -07:00
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
7dd4492abb
First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
2016-09-13 20:30:14 -07:00
cc88bf1b08
junctions: give unit tests more time
2016-09-13 18:33:56 -07:00
44501cdbf8
crossings: change defaults to sync=3 for safer settling time
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Make the matching AsyncQueue depth=8 to support full throughput
2016-09-13 18:33:56 -07:00
3348236320
junctions: remove obsolete Handshaker crossing
2016-09-13 18:33:56 -07:00
d75f9d6a34
junctions: add an AsyncQueue
2016-09-13 17:38:18 -07:00
8142406d2e
junctions: refactor the Crossing type
2016-09-13 15:51:18 -07:00
ecdfb528c5
crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain
2016-09-13 15:51:18 -07:00
05100c12a7
Merge branch 'master' of github.com:ucb-bar/rocket-chip into monitor
2016-09-13 11:18:18 -07:00
606f19a17f
tilelink2: RegisterRouter Unit Test
2016-09-12 22:13:39 -07:00
273d3a73f2
tilelink2: Unit Test passes!
2016-09-12 18:39:50 -07:00
0671d5d637
Initial version of fuzzer and simple ram fuzz test
2016-09-12 10:32:45 -07:00
bb3f514e8d
now able to add periphery devices through traits
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Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
2016-09-10 23:39:29 -07:00
e35e7b2ee3
Fix routing in non-contiguous MMIO regions
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This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
2016-09-07 19:28:12 -07:00
b76612f357
relax contraint on adding AddrMapEntry to AddrMap ( #248 )
...
now you can add them in any order. there's an explicit check at the end to figure out whether there are overlapping regions.
2016-09-06 21:53:55 -07:00
66de89c4db
allow fixed priority routing in Junctions arbiters
2016-09-04 10:55:19 -07:00
efe8670283
allow Serializer/Deserializer to work with arbitrary Chisel data types
2016-09-04 10:55:19 -07:00
b9b79e4fb6
get rid of AtoS RTL
2016-09-04 10:55:19 -07:00
4a7972be31
connect testharness components via member functions ( #236 )
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to prevent code duplication for new testbenches
2016-09-01 18:38:39 -07:00
75efc7dee7
JtagIO's DRV_TDO should be an INPUT
2016-08-19 16:38:03 -07:00
723cc063cb
Move files after the file reorganization
2016-08-19 16:11:41 -07:00
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
