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Commit Graph

17 Commits

Author SHA1 Message Date
Andrew Waterman
fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
Andrew Waterman
ae0716fb6d Use chisel printf for logging 2013-06-13 10:53:23 -07:00
Andrew Waterman
cfa86dba4f add FPGA test bench
The memory models now support back pressure on the response.
2013-05-02 04:59:32 -07:00
Andrew Waterman
d2e1828714 gracefully kill htif thread, fixing tty stuff 2013-05-02 04:59:32 -07:00
Andrew Waterman
def11e44b8 don't pipe stdout to vcd2vpd 2013-03-25 17:01:13 -07:00
Andrew Waterman
c6695bee7c fix emulator HTIF interface bug 2013-02-20 16:11:21 -08:00
Andrew Waterman
dbb61306f0 randomize coreid mapping 2013-01-26 16:13:14 -08:00
Andrew Waterman
4077b22929 include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
Andrew Waterman
d911e635d6 simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
2012-12-04 07:04:26 -08:00
Andrew Waterman
6d47d18c2b catch sigterm to gracefully exit (fixes vcd) 2012-11-20 05:40:44 -08:00
Andrew Waterman
b58214d7e3 remove more global constants 2012-11-17 17:25:43 -08:00
Andrew Waterman
cf05b604b3 upgrade to new rocket; improve vlsi makefiles 2012-11-17 07:21:29 -08:00
Andrew Waterman
e2afae011a factor out global constants 2012-11-06 08:18:40 -08:00
Andrew Waterman
4ed2d614a2 update to new rocket; retime fpu in dc-syn 2012-11-04 16:43:02 -08:00
Andrew Waterman
edf0eeed01 integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
Miquel Moreto
5d75ddc553 Added dramsim2 memory model to the emulator backend 2012-10-14 14:06:28 -07:00
Huy Vo
93a0182b96 everything to get emulator working 2012-10-01 19:30:11 -07:00