Andrew Waterman
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fbdbb01232
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update to new isa; disable vector tests
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2013-09-12 17:04:03 -07:00 |
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Andrew Waterman
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ae0716fb6d
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Use chisel printf for logging
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2013-06-13 10:53:23 -07:00 |
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Andrew Waterman
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cfa86dba4f
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add FPGA test bench
The memory models now support back pressure on the response.
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2013-05-02 04:59:32 -07:00 |
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Andrew Waterman
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d2e1828714
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gracefully kill htif thread, fixing tty stuff
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2013-05-02 04:59:32 -07:00 |
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Andrew Waterman
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def11e44b8
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don't pipe stdout to vcd2vpd
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2013-03-25 17:01:13 -07:00 |
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Andrew Waterman
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c6695bee7c
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fix emulator HTIF interface bug
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2013-02-20 16:11:21 -08:00 |
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Andrew Waterman
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dbb61306f0
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randomize coreid mapping
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2013-01-26 16:13:14 -08:00 |
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Andrew Waterman
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4077b22929
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include fesvr as a library; improve harnesses
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2013-01-24 23:57:23 -08:00 |
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Andrew Waterman
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d911e635d6
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simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
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2012-12-04 07:04:26 -08:00 |
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Andrew Waterman
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6d47d18c2b
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catch sigterm to gracefully exit (fixes vcd)
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2012-11-20 05:40:44 -08:00 |
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Andrew Waterman
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b58214d7e3
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remove more global constants
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2012-11-17 17:25:43 -08:00 |
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Andrew Waterman
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cf05b604b3
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upgrade to new rocket; improve vlsi makefiles
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2012-11-17 07:21:29 -08:00 |
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Andrew Waterman
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e2afae011a
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factor out global constants
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2012-11-06 08:18:40 -08:00 |
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Andrew Waterman
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4ed2d614a2
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update to new rocket; retime fpu in dc-syn
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2012-11-04 16:43:02 -08:00 |
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Andrew Waterman
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edf0eeed01
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integrate updated rocket/uncore
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2012-10-18 17:51:41 -07:00 |
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Miquel Moreto
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5d75ddc553
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Added dramsim2 memory model to the emulator backend
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2012-10-14 14:06:28 -07:00 |
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Huy Vo
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93a0182b96
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everything to get emulator working
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2012-10-01 19:30:11 -07:00 |
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