1
0
Commit Graph

43 Commits

Author SHA1 Message Date
Wesley W. Terpstra
6aeadc4551 regression: disable ComparatorL2Config for now
This tests atomics against the L2.  However, we don't have an L2 yet so this
is hitting the broadcast hub, which does not support these operations.
2016-11-23 20:53:36 -08:00
Henry Cook
837d207064 [travis] split up groundtest into two suites 2016-11-23 12:27:40 -08:00
Wesley W. Terpstra
3d1a7bd6d3 travis: build verilator and toolchain as part of install 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
ea3ec89676 travis: split RocketSuite into three smaller tests suites 2016-11-21 21:13:23 -08:00
Henry Cook
e68795421a remove L2 regressions for now 2016-11-19 20:11:20 -08:00
Megan Wachs
fc4d6ed0c6 jtag: clean up debug flags in regression/Makefile 2016-09-29 13:49:21 -07:00
Megan Wachs
45bd63fcc6 jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec 2016-09-29 13:49:14 -07:00
Megan Wachs
449d689a4e jtag: Connect the JTAG DTM side of the synchronizer! 2016-09-29 13:48:55 -07:00
Henry Cook
7bca99a27a [tilelink2] Add unit test configs to regression 2016-09-28 18:02:04 -07:00
mwachs5
77a0f76289 Cleanup jtag dtm (#342)
* debug: Clean up Debug TransportModule synchronizer

With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.

I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
2016-09-26 11:10:27 -07:00
Henry Cook
91aab2fabc no commas in yml 2016-09-22 17:28:34 -07:00
Henry Cook
83c08a931d [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator 2016-09-22 14:57:18 -07:00
Henry Cook
be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
Henry Cook
888f6a2a55 Revert "move UnitTest back into rocketchip module"
This reverts commit f95b8c4ec2.
2016-09-15 11:48:09 -07:00
Howard Mao
f95b8c4ec2 move UnitTest back into rocketchip module 2016-09-14 20:51:56 -07:00
Yunsup Lee
97809b183f refactor unittest framework
as a result, there's another SUITE that needs to run
2016-09-14 18:10:21 -07:00
Megan Wachs
67467c65f5 Add a jtag-dtm-regression target to the regression
This doesn't get added to Travis, but this target can be used
by other automated testing tools which may want to do further
testing on rocket-chip.
2016-08-23 16:53:50 -07:00
Howard Mao
1c5034707b fix submodules in regression makefile 2016-08-19 13:45:23 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
Howard Mao
163cba6a85 make sure all regressions actually run 2016-08-10 14:52:06 -07:00
Andrew Waterman
2906c75167 Remove fsim, as it is the same as vsim, modulo CONFIG 2016-08-09 15:42:22 -07:00
Howard Mao
63b814fcd7 only run the important (high coverage) tests in regression suite 2016-08-02 10:54:05 -07:00
Howard Mao
6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
Howard Mao
75347eed56 some fixes and cleanup to stateless bridge 2016-07-21 19:51:26 -07:00
Howard Mao
c924ec2a22 fixing bufferless broadcast hub 2016-07-05 12:10:22 -07:00
Howard Mao
39ec927a3f replace complicated pattern substitutions with automatic variable 2016-06-28 18:30:11 -07:00
Howard Mao
800e62412a use the fast version of asm/bmark-tests 2016-06-24 15:36:10 -07:00
Howard Mao
d6ba0437ff merge different configs into regression suites to reduce travis build times 2016-06-24 13:02:29 -07:00
Palmer Dabbelt
f6432395cb Allow the regressions to run more than once 2016-06-14 21:21:44 -07:00
Andrew Waterman
da105a5944 Don't allow travis to recurse through submodules 2016-05-25 13:27:49 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Colin Schmidt
b0ae003981 add firrtl to regression makefile
this makes it easier to test chisel3 builds
e.g. the local buildbot can now test a bunch of configs
2016-05-17 17:34:20 -07:00
Andrew Waterman
8b06947446 Run bmarks faster (hopefully) 2016-05-04 22:47:34 -07:00
Palmer Dabbelt
cddfdf0929 Add CHISEL_VERSION make argument
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3.  Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
Colin Schmidt
b5992186df include top-level makefrag in regressions
fixes issue with rocketchip_addons inclusion
2016-03-16 15:52:28 -07:00
Colin Schmidt
68a49c7700 fetch rocketchip_addons during regression submodule step 2016-02-26 11:05:41 -08:00
Palmer Dabbelt
ad62afd9ca Add zscale to regression submodule list 2016-02-23 12:58:08 -08:00
Palmer Dabbelt
edd0b3b824 Move travis to the regression Makefile
We want to add support for caching riscv-tools builds on Travis and the easiest
way to do so looks like to jus go ahead and use
2016-02-23 10:58:51 -08:00
Palmer Dabbelt
e18759642f Avoid running Chisel in parallel in the same directory
It looks like Chisel fails when I try to run it in parallel.  This adds a lock
file to ensure that only a single Chisel instance is running at a time when
running the regressions.
2016-01-31 23:06:59 -08:00
Palmer Dabbelt
00465b15c3 Allow the regression Makefile to clean all targets 2016-01-31 23:06:59 -08:00
Palmer Dabbelt
c9a2b7d109 Add torture as part of the regression
Since the latest Spike fix my torture runs are succeeding, so I can now run it
as part of the regression flow.
2016-01-31 23:06:59 -08:00
Palmer Dabbelt
e185fe6850 Add targets for emulator and fsim regressions
This change allows the other simulation targets (the emulator and the FPGA
simulator) to be run just like the Verilog simulator could be before.
2016-01-31 23:06:59 -08:00
Palmer Dabbelt
7209c13338 Move to a regression Makefile
In order to have the buildbot support various types of failures it needs
to run different commands.  Rather than modifying the regression script
to have a bunch of arguments I've just gone and made a makefile for
regressions instead.

This doesn't run torture right now because that's broken, but I'll add
support soon.
2016-01-26 22:50:49 -08:00