This change allows the other simulation targets (the emulator and the FPGA simulator) to be run just like the Verilog simulator could be before. |
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.. | ||
.gitignore | ||
Makefile |
This change allows the other simulation targets (the emulator and the FPGA simulator) to be run just like the Verilog simulator could be before. |
||
---|---|---|
.. | ||
.gitignore | ||
Makefile |