Henry Cook
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4af437fdab
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RANDOMIZE_MEM_INIT vlsi_mem_gen (#572)
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2017-03-07 01:56:15 -08:00 |
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GuzTech
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8157cf1ede
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Perform integer division when parsing rocketchip.DefaultConfig.conf (#493)
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2017-01-13 16:40:02 -08:00 |
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Colin Schmidt
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92718e4b61
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fix null statement in vsli_mem_gen ala firrtl#264 (#252)
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2016-09-07 11:04:36 -07:00 |
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Megan Wachs
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48098f5e2d
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Bump FIRRTL to instantiate Sequential Memory Macros
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2016-09-06 14:48:28 -07:00 |
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Henry Cook
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d3ccec1044
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Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
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2015-07-02 14:43:30 -07:00 |
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Schuyler Eldridge
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b4cd8c5981
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Fix vlsi_mem_gen for Python 2 or 3
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2015-06-25 12:48:31 -07:00 |
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Yunsup Lee
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1cfd9f5a0e
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add LICENSE
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2014-09-12 10:15:04 -07:00 |
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Yunsup Lee
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ddfd3ce968
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further generalize fpga/vlsi builds
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2014-09-08 00:21:57 -07:00 |
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Yunsup Lee
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1cb2d1d7b7
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initialize all SRAMs to avoid X propagation problem
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2014-09-04 11:06:01 -07:00 |
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Yunsup Lee
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c03c09ec31
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update for rocket-chip release
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2014-08-31 20:26:55 -07:00 |
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