Megan Wachs
fd7f4a4c0f
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
Megan Wachs
d2c1bdc2ce
Debug Controls ( #639 )
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* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.
* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
2017-04-03 13:31:35 -07:00
Megan Wachs
42ca597478
debug: Breaking change until FESVR is updated as well.
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* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
Wesley W. Terpstra
ac205ca10a
bootrom: move to 0x10000 for more space (DTB on multicore is big)
2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
34f8ce653a
bootrom: follow SBI (a0=hartid, a1=dtb)
2017-03-24 18:18:01 -07:00
Henry Cook
a281ad8ad2
rocketchip: rename some periphery ports
2017-02-23 18:28:04 -08:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
4b9dc78951
rocketchip: add a parameter-controlled debug port
2016-11-23 15:35:53 -08:00
Wesley W. Terpstra
37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
10e459fedb
rocket: change connection between rocketchip and coreplex
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* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
