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Commit Graph

18 Commits

Author SHA1 Message Date
Andrew Waterman
725190d0ee update to new chisel 2012-02-11 17:20:33 -08:00
Henry Cook
c5a4eaa0a1 Associative cache, boots kernel 2012-02-01 13:26:04 -08:00
Henry Cook
281abfbccb New Mux1H constructor 2012-02-01 13:24:28 -08:00
Andrew Waterman
97c379f1d7 made I$ associative 2012-01-24 16:51:30 -08:00
Henry Cook
aa3465699b LFSR now a util 2012-01-24 15:26:19 -08:00
Henry Cook
8766438bb9 Updated chisel removes ^^ from language. Removed from rocket source, updated jar. 2012-01-23 17:09:23 -08:00
Henry Cook
97f0852b17 DM cache with assoc-aware subunits passes all asm and bmarks 2012-01-18 17:53:26 -08:00
Henry Cook
29ed8eb31a More utils for nbdcache 2012-01-18 17:09:35 -08:00
Henry Cook
7e25749581 Groundwork for assoc cache implementation 2012-01-18 17:09:35 -08:00
Henry Cook
1d76255dc1 new chisel version jar and find and replace INPUT and OUTPUT 2012-01-18 14:39:57 -08:00
Andrew Waterman
d65e1a2eee vlsi verilog compiles now but doesn't simulate 2011-12-20 22:08:27 -08:00
Andrew Waterman
96c78829b4 improve ALU and fix revealed emulator bug 2011-12-17 07:20:32 -08:00
Andrew Waterman
a8d0cd95e6 hellacache now works 2011-12-17 03:26:11 -08:00
Andrew Waterman
56c4f44c2a hellacache returns!
but AMOs are unimplemented.
2011-12-12 06:49:39 -08:00
Andrew Waterman
8308345364 work in progress on hellacache 2011-12-10 07:01:47 -08:00
Andrew Waterman
218f63e66e code cleanup/parameterization 2011-12-09 00:42:43 -08:00
Rimas Avizienis
f86d5b1334 cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB 2011-11-10 11:26:13 -08:00
Rimas Avizienis
e96430d862 integrating ITLB & PTW 2011-11-09 14:52:17 -08:00