Andrew Waterman
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725190d0ee
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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Henry Cook
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c5a4eaa0a1
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Associative cache, boots kernel
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2012-02-01 13:26:04 -08:00 |
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Henry Cook
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281abfbccb
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New Mux1H constructor
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2012-02-01 13:24:28 -08:00 |
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Andrew Waterman
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97c379f1d7
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made I$ associative
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2012-01-24 16:51:30 -08:00 |
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Henry Cook
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aa3465699b
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LFSR now a util
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2012-01-24 15:26:19 -08:00 |
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Henry Cook
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8766438bb9
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Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
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2012-01-23 17:09:23 -08:00 |
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Henry Cook
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97f0852b17
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DM cache with assoc-aware subunits passes all asm and bmarks
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2012-01-18 17:53:26 -08:00 |
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Henry Cook
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29ed8eb31a
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More utils for nbdcache
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2012-01-18 17:09:35 -08:00 |
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Henry Cook
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7e25749581
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Groundwork for assoc cache implementation
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2012-01-18 17:09:35 -08:00 |
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Henry Cook
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1d76255dc1
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new chisel version jar and find and replace INPUT and OUTPUT
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2012-01-18 14:39:57 -08:00 |
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Andrew Waterman
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d65e1a2eee
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vlsi verilog compiles now but doesn't simulate
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2011-12-20 22:08:27 -08:00 |
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Andrew Waterman
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96c78829b4
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improve ALU and fix revealed emulator bug
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2011-12-17 07:20:32 -08:00 |
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Andrew Waterman
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a8d0cd95e6
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hellacache now works
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2011-12-17 03:26:11 -08:00 |
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Andrew Waterman
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56c4f44c2a
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hellacache returns!
but AMOs are unimplemented.
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2011-12-12 06:49:39 -08:00 |
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Andrew Waterman
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8308345364
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work in progress on hellacache
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2011-12-10 07:01:47 -08:00 |
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Andrew Waterman
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218f63e66e
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code cleanup/parameterization
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2011-12-09 00:42:43 -08:00 |
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Rimas Avizienis
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f86d5b1334
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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