Andrew Waterman
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a87ad06780
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Automatically infer rocketCAM address width
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2011-12-06 02:05:40 -08:00 |
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Rimas Avizienis
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5a322ff00c
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fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions
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2011-11-17 11:17:37 -08:00 |
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Rimas Avizienis
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ae98956e6b
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more amo fixes, added more options to testharness to control debug messages
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2011-11-15 02:43:51 -08:00 |
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Rimas Avizienis
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9d3471a569
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more cache fixes, more test harness debug output
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2011-11-13 23:32:18 -08:00 |
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Rimas Avizienis
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fbd44ea936
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added checks for addresses > physical memory size, increased memsize to 64M
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2011-11-12 23:39:43 -08:00 |
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Rimas Avizienis
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91c252ad08
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fixing output enable signals for data/tag SRAMs
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2011-11-12 15:47:47 -08:00 |
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Rimas Avizienis
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83d90c4dab
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more itlb/dtlb/ptw fixes
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2011-11-12 15:00:45 -08:00 |
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Rimas Avizienis
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44926866b7
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updated itlb
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2011-11-11 18:48:34 -08:00 |
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Rimas Avizienis
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a1ce908541
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dcache/dtlb overhaul
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2011-11-11 18:18:47 -08:00 |
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Rimas Avizienis
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e4fa94aa27
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checkpoint
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2011-11-10 17:41:22 -08:00 |
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Rimas Avizienis
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f86d5b1334
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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36aa4bcc9d
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moved exception handling from ex stage in dpath to mem stage in ctrl
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2011-11-10 02:26:26 -08:00 |
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Rimas Avizienis
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62407b4668
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more tlb/ptw fixes
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2011-11-10 00:23:29 -08:00 |
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Rimas Avizienis
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c29d2821b4
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cleanup, fixes, initial commit for dtlb.scala
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2011-11-09 21:54:11 -08:00 |
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