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riscv/rocket-chip
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733 Commits 1 Branch 0 Tags
2086c0d6036c8ee300ab9c97c2934293e42f3794
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Author SHA1 Message Date
Wesley W. Terpstra 2086c0d603 Configs: add a parameter to control the memory subsystem interface 2016-06-06 21:35:43 -07:00
Wesley W. Terpstra 2ddada1732 ahb: add mmio_ahb option 2016-06-06 21:35:39 -07:00
Wesley W. Terpstra 31f1dcaf84 ahb: rename mmio outputs to mmio_axi 2016-06-06 21:35:34 -07:00
Wesley W. Terpstra 7a24527448 ahb: make MMIO channels specifiy bus type (we will have more than one bridge) 2016-06-06 21:35:30 -07:00
Wesley W. Terpstra f3a557b67b ahb: AHB parameters should be site specific
Conflicts:
	src/main/scala/Configs.scala
2016-06-06 21:35:24 -07:00
Wesley W. Terpstra 976d4d3184 ahb: AHB parameters should match TileLink parameters by default
Closes #116
2016-05-25 18:01:25 -07:00
Wesley W. Terpstra da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
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