Wesley W. Terpstra
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9ca8f514c0
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rocket: creating Bundles in an object also break dedup!
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2017-01-31 14:45:11 -08:00 |
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Wesley W. Terpstra
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e1577bb06e
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chisel3: bump chisel3 for work deduplication
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2017-01-31 14:20:07 -08:00 |
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Wesley W. Terpstra
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e5af59db68
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rocketchip: work-around ucb-bar/chisel3#472
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2017-01-31 14:20:02 -08:00 |
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Wesley W. Terpstra
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9c0cc6fdf4
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Merge pull request #537 from ucb-bar/l2-banks-together
BankedL2Config: use the same LazyModule for all L2 banks
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2017-01-30 15:39:04 -08:00 |
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Wesley W. Terpstra
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dc66c8857f
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diplomacy: be more robust using Java introspection
If an error occures, some objects might only be partially initialized.
We want to still be able to get nice names for error messages.
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2017-01-30 14:25:12 -08:00 |
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Wesley W. Terpstra
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280af9684b
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BankedL2Config: use the same LazyModule for all L2 banks
This makes it much easier for banked coherence managers to support
cross-bank functionality, like a common control port, for example.
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2017-01-30 14:02:59 -08:00 |
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Henry Cook
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b567a2a356
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Merge pull request #536 from ucb-bar/diplomacy-star-nodes
diplomacy: add :*= and :=* to support flexible # of edges
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2017-01-30 11:19:33 -08:00 |
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Wesley W. Terpstra
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f7f52cc722
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diplomacy: restore Monitor functionality
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2017-01-29 17:25:14 -08:00 |
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Wesley W. Terpstra
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972953868c
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uncore: switch to new diplomacy Node API
Most adapters should work on multiple ports.
This patch changes them all.
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2017-01-29 15:54:45 -08:00 |
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Wesley W. Terpstra
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4d646939b0
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diplomacy: make flexible-port adapters possible
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2017-01-29 14:26:02 -08:00 |
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Wesley W. Terpstra
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24ee7f45f5
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rocketchip: pass variable l1tol2 connections into coreplex
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2017-01-29 11:18:36 -08:00 |
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Wesley W. Terpstra
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d5fa159063
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diplomacy: add :*= and :=* to support flexible # of edges
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2017-01-28 21:32:36 -08:00 |
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Wesley W. Terpstra
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03f2fe02ac
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coreplex: support rational crossing to L2 (#534)
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2017-01-27 17:09:43 -08:00 |
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Richard Xia
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61fbe62112
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Ignore the built firrtl.jar. (#532)
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2017-01-27 13:04:15 -08:00 |
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Wesley W. Terpstra
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19c58630d2
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Merge pull request #533 from ucb-bar/rational-crossing
Rational clock crossing
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2017-01-26 22:30:04 -08:00 |
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Wesley W. Terpstra
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830d01329d
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RationalCrossing: add some documentation
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2017-01-26 21:27:34 -08:00 |
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Wesley W. Terpstra
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fc3b72084f
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tilelink2: add a rational clock crossing adapter
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2017-01-26 20:07:28 -08:00 |
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Wesley W. Terpstra
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4b70386393
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AsyncCrossing: disambiguate the file name
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2017-01-26 20:07:28 -08:00 |
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Wesley W. Terpstra
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5cf4b0632d
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RationalCrossing: clock crossing between related clock domains
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2017-01-26 20:07:28 -08:00 |
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Jack Koenig
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1285fa909f
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Bump chisel and firrtl (#531)
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2017-01-26 17:29:26 -08:00 |
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Jim Lawson
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3c1dac8c68
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Match chisel3 userootunmanageddir - use RootProject/lib as unmanagedBase. (#526)
This anticipates ucb-bar/chisel3#448. When rocket-chip uses that version of chisel3, the extra copy to chisel3/lib may be removed.
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2017-01-26 11:11:14 -08:00 |
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Henry Cook
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0fe2899c74
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[tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528)
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2017-01-25 12:10:49 -08:00 |
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Wesley W. Terpstra
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d1dedd25e7
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Merge pull request #529 from ucb-bar/physical-optimization
Physical optimization
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2017-01-24 18:59:07 -08:00 |
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Wesley W. Terpstra
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6ff35a387a
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tilelink2: disable A=>D bypass in ToAXI4 whenever possible
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2017-01-24 18:11:00 -08:00 |
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Wesley W. Terpstra
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64e1de751d
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axi4: add a minLatency parameter
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2017-01-24 18:11:00 -08:00 |
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Wesley W. Terpstra
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46cdfc2b45
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diplomacy: find names of LazyModules also in Seq() member values (#527)
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2017-01-24 18:10:37 -08:00 |
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Wesley W. Terpstra
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3fc55298ef
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coreplex: provide coherence managers with geometry information
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2017-01-23 15:50:39 -08:00 |
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Wesley W. Terpstra
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d4b3a0f0be
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diplomacy: support given bits in AddressDecoder
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2017-01-23 15:50:39 -08:00 |
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Wesley W. Terpstra
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c0b6d31377
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tilelink2: Delayer adapter useful for unit tests
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2017-01-23 15:50:39 -08:00 |
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Wesley W. Terpstra
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b3ef146805
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Merge pull request #523 from ucb-bar/buffer-move
coreplex: move TLBuffers for L2 and socBus
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2017-01-21 14:53:51 -08:00 |
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Wesley W. Terpstra
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38c9ddffcc
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BankedL2: move TLFilter BEFORE coherence manager
This lets smart caches exclude the sets that are filtered.
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2017-01-21 13:23:07 -08:00 |
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Wesley W. Terpstra
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dcadd5a006
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coreplex: move TLBuffers for L2 and socBus
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2017-01-20 22:23:36 -08:00 |
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Wesley W. Terpstra
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e8ce32a156
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Merge pull request #515 from ucb-bar/cache-cork
Cache cork
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2017-01-19 20:00:51 -08:00 |
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Wesley W. Terpstra
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9dc7f180b6
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diplomacy: support zero-port Nodes
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2017-01-19 19:08:01 -08:00 |
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Wesley W. Terpstra
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c0496fab29
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regression: disable build that times out on Travis
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2017-01-19 19:07:59 -08:00 |
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Wesley W. Terpstra
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5d70265e86
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rocket: L1 only needs cache-line transfer sizes
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2017-01-19 19:07:14 -08:00 |
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Wesley W. Terpstra
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3a5e5a65f8
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coreplex: support multiple memory channels via diplomatic trickery
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2017-01-19 19:07:14 -08:00 |
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Wesley W. Terpstra
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e7b35b4bb6
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diplomacy: support multiple ports behind a BlindNode
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2017-01-19 19:07:14 -08:00 |
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Wesley W. Terpstra
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258abc5629
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coreplex: re-enable stateless L2 config
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2017-01-19 19:07:14 -08:00 |
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Wesley W. Terpstra
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4bdb2e5d68
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tilelink2 Monitor: ReleaseAck source does not count
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2017-01-19 19:07:14 -08:00 |
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Wesley W. Terpstra
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fbf1073586
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tilelink2: CacheCork - terminate caching
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2017-01-19 19:07:14 -08:00 |
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Wesley W. Terpstra
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bf7823f1c8
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tilelink2: split suportsAcquire into T and B variants
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2017-01-19 19:07:13 -08:00 |
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Henry Cook
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e03ba637f4
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[regression] remove FancyMemTest (timing out)
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2017-01-19 17:48:04 -08:00 |
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Henry Cook
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c1b7c84f09
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[rocket] bugfix: RoccExampleConfig looks up PAddrBits too early
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2017-01-19 17:48:04 -08:00 |
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Henry Cook
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e0411c6cde
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[coreplex] bugfix: re-enable multicore configs via WithNCores
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2017-01-19 17:48:04 -08:00 |
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Henry Cook
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307f938b88
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[rocket] bugfix: fixes #517
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2017-01-19 17:48:04 -08:00 |
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Megan Wachs
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4fe75965a0
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Merge pull request #518 from ucb-bar/dtm_regression
jtag_dtm: Update regression to run and pass.
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2017-01-18 14:39:53 -08:00 |
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Megan Wachs
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e22b01a6fa
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jtag_dtm: Update regression to run and pass.
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2017-01-18 12:08:13 -08:00 |
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Henry Cook
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1b31dfa700
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Update sbt to 13.12 (#514)
Closes #496
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2017-01-17 16:26:22 -08:00 |
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Henry Cook
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9a6634cd40
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Add TLBuffers on the L1 backends and blind exit points (#513)
* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
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2017-01-17 11:57:23 -08:00 |
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