94f06dc85c
pbus: turn down overkill buffering between PBus and SBus
2017-09-05 15:03:38 -07:00
c353f68dc0
buses: name dummy buffers too
2017-09-05 15:03:38 -07:00
3bde9506c6
coreplex: allow buffer chains on certain bus ports
2017-09-05 15:03:36 -07:00
57d0360c35
frontbus: Name the connection.
2017-08-30 18:07:34 -07:00
c99afe4c66
buses: Name all the things.
2017-08-30 17:31:42 -07:00
32cb358c81
coreplex: include optional tile name for downstream name stabilization
2017-08-30 15:48:55 -07:00
183fefb2b9
Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in
2017-08-30 15:27:56 -07:00
d5b62dffda
SystemBus: add stupidly many (4 more) buffers from sbus=>pbus
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This should probably be reverted.
2017-08-30 14:22:49 -07:00
f7330028cc
Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter
2017-08-30 14:22:49 -07:00
173f185b17
Merge pull request #976 from freechipsproject/system-buffer
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SystemBus: add output buffering
2017-08-30 23:22:13 +02:00
656609d610
SystemBus: split FIFOFixers along bus boundaries
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If you have a system with a lot of periphery slaves, you wan to FIFO fix
them on the periphery bus rather than paying the circuit cost at the sbus.
2017-08-30 13:28:11 -07:00
a3bc5f2e33
synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive
2017-08-30 12:59:16 -07:00
8139014c9e
syncrhonizers: Remove unused sync from superclass
2017-08-30 12:33:03 -07:00
9dd6c4c32d
synchronizers: New chisel ways of cloning type and use simpler lambda function
2017-08-30 12:11:14 -07:00
bd32f0c122
synchronizers: properly pass parameters up to the superclass
2017-08-30 11:58:25 -07:00
483e63da19
synchronizers: Correctly pass the width through
2017-08-30 11:50:25 -07:00
a62ce0afe6
TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer.
2017-08-29 10:36:46 -07:00
c473538e36
Merge remote-tracking branch 'origin/master' into async_reg
2017-08-28 17:19:03 -07:00
451334ac73
Add 1-deep synchronizer register for output of AsyncQueue
2017-08-28 17:18:54 -07:00
bf19440db5
SystemBus: use a full buffer on slaves
2017-08-26 02:47:04 -07:00
85c39b2f97
syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI
2017-08-24 17:47:04 -07:00
4e773f4738
syncregs: Use synchronizer primivites for LevelSyncCrossing
2017-08-24 17:42:31 -07:00
130b24355f
syncregs: Use synchronizer primitives for IntXing
2017-08-24 17:39:07 -07:00
8b462d1595
syncregs: Use common primitives for AsyncQueue grey code synchronizers
2017-08-24 17:34:07 -07:00
3461cb47cc
syncregs: Make Reset catcher use the synchronizer primitive
2017-08-24 17:26:38 -07:00
c78ee9f0e4
syncreg: Refactor common code
2017-08-24 17:18:04 -07:00
d83a6dc6af
syncregs: Add utilities for Synchronizing Shift Registers
2017-08-24 16:55:17 -07:00
7f683eeb24
async_regs: Make modules have predictable names
2017-08-24 15:33:53 -07:00
0f75ebee92
async_reg: Rename the file to match scalastyle
2017-08-24 15:31:29 -07:00
103b6bc6d3
systemBus: allowing naming the TLBuffers which get inserted
2017-08-24 14:49:12 -07:00
17134125e1
SystemBus: remove misnamed functions ( #972 )
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These functions were actually for cross connecting chips.
2017-08-24 23:35:01 +02:00
82df766f4a
Merge pull request #963 from freechipsproject/interrupt-order
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Respect ISA requirements on interrupt priority order
2017-08-18 00:10:19 -07:00
8087a205cc
Remove redundant check in interrupt priority encoding
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chooseInterrupts already sorts M interrupts above S interrupts.
2017-08-17 22:23:42 -07:00
cbe7c51b50
Respect ISA requirements on interrupt priority order
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https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3
2017-08-17 21:27:08 -07:00
b1719cfee0
Fixing requirements for PAddrBits ( #961 )
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Previously, the requirement for PAddrBits only checked to be equal or greater than the bundle bits. Changing it to check for these to match exactly as for cases when the PAddrBits greater than address bits we could run into scenarios which cause possible address wrap around issues.
2017-08-17 11:53:59 -07:00
1db4b3be9a
Merge pull request #957 from freechipsproject/param_jtag_vpi
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jtag_vpi: Use Parameterized Black Box
2017-08-14 18:37:30 -07:00
8783d51c97
jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed
2017-08-14 17:25:47 -07:00
710a782145
HeterogenousBag: empty bags were being combined! ( #956 )
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This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.
2017-08-14 15:48:42 -07:00
e945f6e265
Merge pull request #955 from freechipsproject/fix-acquire-before-release
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Fix acquire before release
2017-08-13 18:29:58 -07:00
88332bd885
max-core-cycles: Add a +max-core-cycles PlusArg
2017-08-13 15:47:14 -07:00
3cbc5262ec
Don't permit new acquires until the release queue is drained
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If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
2017-08-13 13:18:45 -07:00
0190724492
Actually use the C-channel acquire-before-release queue
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oops...
2017-08-13 13:03:35 -07:00
7387f2a93a
Don't block D-channel when handling a probe
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This is an acquire-before-release regression.
2017-08-12 16:13:24 -07:00
604abd5b07
Only report ECC errors when the RAM was actually read
2017-08-12 15:28:03 -07:00
18fb052fc9
DRY
2017-08-12 15:27:30 -07:00
176110b6d3
Don't trigger ECC writebacks when a release is in flight
2017-08-12 15:23:57 -07:00
f191bb994c
PatternPusher: can now expect a certain output ( #952 )
2017-08-11 18:10:27 -07:00
baf769f924
tilelink: add PatternPusher, a device to inject a fixed traffic pattern ( #950 )
2017-08-11 15:07:10 -07:00
a3358f34a0
Fix priority inversion for two back-to-back divides ( #948 )
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If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit. While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
2017-08-10 17:12:09 -07:00
0a591c5b5b
Roll back use of UIntToOH1 ( #946 )
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These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass. This is not yet conclusive.
2017-08-09 18:39:47 -07:00
Megan Wachs
Henry Cook
Wesley W. Terpstra
Henry Styles
Andrew Waterman
Andrew Waterman
Shreesha Srinath