15dc7f6760
JTAGVPI: remove it from Chisel as it is unused
2018-03-07 10:55:45 -08:00
bd3a72e585
Merge remote-tracking branch 'origin/master' into sim_jtag_reset
2018-03-05 12:41:39 -08:00
5eae81038d
SimJTAG: make the reset/init connectivity more flexible. This is because you may want to seperate the two
2018-03-02 17:29:17 -08:00
030c6f0206
subsystem: bus wrappers now in BaseSubsystem
2018-02-21 14:52:59 -08:00
3f436a7612
subsystem: new bus attachment api
2018-02-21 14:43:47 -08:00
8462ea3d5b
coreplex => subsystem
2018-02-21 14:42:24 -08:00
bd29184e11
debug: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
e6661a6982
Debug regressions: use a plusarg to enable remote bitbang.
2018-01-05 17:08:21 -08:00
4449dd0baa
Debug regressions: Add necessary config scripts
2018-01-05 16:03:59 -08:00
9217baf9d4
diplomacy: change API to auto-create node bundles => cross-module refs
2017-09-22 15:01:39 -07:00
c85333f826
Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset
2017-09-17 13:51:46 -07:00
215e072e5c
test_mode_reset: fix typos
2017-09-17 13:51:40 -07:00
9b75dd7e5b
Merge branch 'master' into test_mode_reset
2017-09-15 17:26:11 -07:00
641a8e7eab
test_mode_reset: Correct some gender issues. Tie off signals in the test harness
2017-09-15 16:36:35 -07:00
6cda4504ac
test_mode_reset: use a cleaner interface with bundles and options instead of individual signals
2017-09-15 12:30:39 -07:00
a0396b63e8
test_mode_reset: fix one bulk-connect gender issue
2017-09-14 13:16:13 -07:00
82c00cb656
reset_catch: Allow Test Mode Overrides
2017-09-14 13:16:13 -07:00
b86f4b9bb7
config: use Field defaults over Config defaults
...
Also rename some keys that had the same class name as their value's class name.
2017-09-13 11:25:42 -07:00
8783d51c97
jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed
2017-08-14 17:25:47 -07:00
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
...
* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
Megan Wachs
Henry Cook
Andrew Waterman
Wesley W. Terpstra