riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,715 Commits 1 Branch 0 Tags 13 MiB
0ef45fac9b
Commit Graph

4715 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andrew Waterman
0ef45fac9b Add tag ECC to D$ 2017-07-03 18:16:37 -07:00
Andrew Waterman
e9752f76ae Improve probe state machine 
- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
 2017-07-03 16:25:04 -07:00
Megan Wachs
85f37146d5 Merge pull request #842 from freechipsproject/fesvr-multi 
Bump FESVR for multi-core support
 2017-07-03 15:31:41 -07:00
Megan Wachs
ddd2b2236d bump riscv-tools/riscv-fesvr to pick up multicore fixes 2017-07-03 13:25:05 -07:00
Megan Wachs
3d28c0182d travis: add a branch whitelist with just 'master'. 
Travis allows us to build on branch updates and on PRs. Right now our process is to build always on PRs, but to manually only build 'master' when we know that riscv-tools has been bumped (because that rebuilds the master cache which holds riscv-tools). But this is an annoying and error-prone processes that requires extra admin permissions.

With this change, i think we can just leave "Build Branch Updates" to "ON" and get the same effect we are currently doing manually, because only on update to master branch will it do a build. PRs to master branch will get a build. PRs to other branches will I believe NOT get a build.
 2017-07-03 13:25:05 -07:00
Richard Xia
ee9789eb68 Merge pull request #840 from freechipsproject/fix-dcache-exception-assignment-order 
Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
 2017-06-30 18:50:49 -07:00
Richard Xia
5b46350bc3 Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment. 2017-06-30 17:44:16 -07:00
Megan Wachs
69ab3626ca Merge pull request #837 from freechipsproject/plic_recode 
plic: Recode to use OH knowledge
 2017-06-30 16:05:32 -07:00
Megan Wachs
8c92c50d85 plic: make assertion comment right 2017-06-30 14:25:09 -07:00
Megan Wachs
f31ae008f3 plic: Clean up comments and simplify checking 2017-06-30 14:15:26 -07:00
Megan Wachs
76f8de75e3 plic: comment tidying 2017-06-30 12:51:09 -07:00
Megan Wachs
3da26b0aa8 plic: Add some assertions to check one-hot assumptions 2017-06-30 12:32:58 -07:00
Ben Keller
85ac8d588c Excise the last instance of run-bmarks-test (#836) 2017-06-30 11:50:40 -07:00
Megan Wachs
237689b799 Merge pull request #838 from freechipsproject/more_plic 
plic: Use same recoding technique on complete as well as claim
 2017-06-30 11:06:27 -07:00
Wesley W. Terpstra
367d4aebe6 Set complete unconditionally 2017-06-30 10:15:53 -07:00
Wesley W. Terpstra
4e9f65b2ef Simplify logic further and bugfix 
complete was being set unconditionally
 2017-06-30 10:07:39 -07:00
Megan Wachs
e8e709c941 plic: Use same recoding technique on complete as well as claim 2017-06-30 08:36:00 -07:00
Wesley W. Terpstra
3dca2bc4a3 gah 2017-06-30 01:07:29 -07:00
Wesley W. Terpstra
e43b7accf9 Fix compile error and eliminate wasteful wires 2017-06-30 01:06:02 -07:00
Megan Wachs
834bcf6b7e PLIC: simplify some scala code 2017-06-29 19:35:15 -07:00
Megan Wachs
eae4fe1469 plic: Recode to use the knowledge that only one interrupt can be claimed at a time. 2017-06-29 19:09:57 -07:00
Wesley W. Terpstra
e3c7bb3b1f SRAM: MemoryDevices use .reg (not .reg("mem")) (#835) 2017-06-29 19:07:12 -07:00
Megan Wachs
ae6971b6db Merge pull request #834 from freechipsproject/resumereq-race 
debug: Fix race between resumereq and resumeack
 2017-06-29 13:38:20 -07:00
Megan Wachs
0668f13d99 debug: Fix race between resumereq and resumeack 
For an arbitrary DMI master on a fast clock running against a core
on a slow clock, there was a race between writing resumereq and
reading resumeack. When using JTAG DTM this does not occur in practice,
but clean it up for running simulations with FESVR and future DMI masters.
 2017-06-29 12:27:23 -07:00
Wesley W. Terpstra
7dae3388e1 Merge pull request #830 from freechipsproject/flip-dts-idtim 
Flip dts itim and dtim references
 2017-06-29 00:18:19 -07:00
Wesley W. Terpstra
5edc4546e3 rocket: add dtim and itim refs to cpus 2017-06-28 23:10:58 -07:00
Wesley W. Terpstra
7d6f8d48f2 Revert "rocket: link dtim to its cpu" 
This reverts commit e6c2d446cc.
 2017-06-28 23:10:57 -07:00
Wesley W. Terpstra
fbcd6f0eb2 Revert "rocket: link itim to its cpu" 
This reverts commit 48390ed604.
 2017-06-28 23:10:57 -07:00
Henry Cook
6e5a4c687f diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
Megan Wachs
992b480c74 Merge pull request #825 from freechipsproject/debug_wfi 
Debug + WFI Interactions
 2017-06-28 21:28:51 -07:00
Wesley W. Terpstra
5002d2accf Merge pull request #827 from freechipsproject/dts-improvements 
Dts improvements
 2017-06-28 17:45:06 -07:00
Megan Wachs
39b06a917f bump riscv-tools for fesvr-dont-die 2017-06-28 16:38:02 -07:00
Wesley W. Terpstra
66489ffa13 rom+sram: add a compatible field 2017-06-28 15:41:20 -07:00
Wesley W. Terpstra
ca3030cba3 dcache: fix a gender inversion bug introduced in #826 2017-06-28 15:38:53 -07:00
Wesley W. Terpstra
02aa80a958 TLZero: include a version number 2017-06-28 15:12:46 -07:00
Wesley W. Terpstra
48390ed604 rocket: link itim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
e6c2d446cc rocket: link dtim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
3f6d5110cd rocket: dtim is not a dcache 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
bca3db0866 diplomacy: add RWXC permissions also to ResourceMappings 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
5436be54ff periphery: use SimpleBus for mmio ports 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
171e1a4c05 diplomacy: add SimpleBus to describe bridges 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
84dc23c215 devices: add reg-names to most devices 2017-06-28 15:06:16 -07:00
Wesley W. Terpstra
0bf46edb6c diplomacy: support reg-names in DTS output 2017-06-28 14:26:55 -07:00
Wesley W. Terpstra
852f03282f rocket: give itim and dtim a compatible field for drivers to match 2017-06-28 14:26:55 -07:00
Wesley W. Terpstra
6c2b770605 plic: do not output #address-cells 
This is only needed for an interrupt-map, not an interrupt-controller.
 2017-06-28 14:26:55 -07:00
Andrew Waterman
936096dd42 Merge pull request #826 from freechipsproject/tlb2 
Various memory system improvements
 2017-06-28 13:51:24 -07:00
Megan Wachs
35b89d8023 bump riscv-tools for fesvr-don't-die 2017-06-28 13:36:53 -07:00
Andrew Waterman
b9a934ae28 Support eccBytes > 1 2017-06-28 02:09:18 -07:00
Andrew Waterman
8e4be40efc Propagate wb_reg_rs2 for sfence ASID 
This would have been a bug if we supported ASIDs.
 2017-06-28 02:09:18 -07:00
Andrew Waterman
2077e4190b Make log more sensible for long-latency operations 
Show only one write to the destination register, not two.
 2017-06-28 02:09:18 -07:00