Wesley W. Terpstra
a5b8fc2317
RegisterRouterTest: start up with 0 in registers to make VIP testing easier
2016-12-14 15:38:08 -08:00
Wesley W. Terpstra
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
...
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
b5f5ef69c1
regmapper: eliminate race condition in RegisterCrossing bypass
2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
52c1a053ff
tilelink2 RegisterRouter: test fully Decoupled behaviour
2016-10-02 02:24:02 -07:00
Henry Cook
69e121260e
[tilelink2] Add unit tests for many TL2 components
...
These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
2016-09-28 18:02:04 -07:00
Henry Cook
81123f84c9
[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. ( #356 )
2016-09-27 18:06:21 -07:00
Wesley W. Terpstra
5e34b313ee
RegMapper: regmap(...) now takes BYTE addresses
...
If a device has configurable bus-width, we need a stable way of
enumerating registers. The byte offset stays unchanged.
This change also makes it possible to put an arbitrary number of RegFields
starting at some address which are then chopped up into appropriately bus-
sized registers.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
05beb20dc4
tilelink2: specify the minLatency for SRAM+RR
2016-09-22 15:18:54 -07:00
Howard Mao
cd96a66ba6
replace verilog clock divider with one written in Chisel
2016-09-22 11:32:29 -07:00
Wesley W. Terpstra
f0f553f227
tilelink2 RegisterRouterTest: work around firrtl warning
...
Using io.wready leads to verilog that reads from the output...
Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
Port "io_wready" declared as output in module "RRTestCombinational_29" may
need to be inout. Coercing to inout.
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
3fcc1a4460
tilelink2 RegisterRouterTest: don't couple fire into helpers
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
1c7d7f9d32
tilelink2 RegisterRouterTest: stall on both edges
2016-09-14 18:22:12 -07:00
Henry Cook
e02d149cbe
[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
2016-09-14 17:43:07 -07:00
Wesley W. Terpstra
d23ab7370d
tilelink2: Unit Test for the RegisterCrossing
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
606f19a17f
tilelink2: RegisterRouter Unit Test
2016-09-12 22:13:39 -07:00
Wesley W. Terpstra
7760459b76
tilelink2 RegisterRouter: add RegField test patterns
2016-09-12 10:32:25 -07:00
