riscv/rocket-chip
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19 Commits

Author SHA1 Message Date
Wesley W. Terpstra
bb6108abd5 Tests: include more random delays 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
9a5e2e038b uncore: add DTS meta-data for devices 2017-03-02 21:19:22 -08:00
Andrew Waterman
dfa61bc487 Standardize Data.holdUnless and SeqMem.readAndHold 
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
  use of holdUnless
 2017-02-25 03:07:49 -08:00
Wesley W. Terpstra
972953868c uncore: switch to new diplomacy Node API 
Most adapters should work on multiple ports.
This patch changes them all.
 2017-01-29 15:54:45 -08:00
Wesley W. Terpstra
020fbe8be9 diplomacy: make config.Parameters available in bundle connect() 
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
 2016-12-07 12:24:01 -08:00
Wesley W. Terpstra
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
c0b27999ea tilelink2 SourceShrinker: a concurrency reducing adapter 2016-11-22 21:43:38 -08:00
Andrew Waterman
e45b41b4b6 Don't rely on SeqMem output after read-enable is low 2016-10-27 23:44:10 -07:00
Wesley W. Terpstra
a82cfb8306 tilelink2: replace addr_hi with address (#397) 
When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
 2016-10-14 14:09:39 -07:00
Wesley W. Terpstra
f05298d9bc tilelink2: move general-purpose code out of tilelink2 package 2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
c85e42a303 tilelink2: Nodes should accept full PortParameters 
We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
 2016-10-03 16:09:49 -07:00
Henry Cook
69e121260e [tilelink2] Add unit tests for many TL2 components 
These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
 2016-09-28 18:02:04 -07:00
Wesley W. Terpstra
05beb20dc4 tilelink2: specify the minLatency for SRAM+RR 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
6c3269a1d8 SRAM: optionally (default: true) executable 2016-09-17 00:19:37 -07:00
Wesley W. Terpstra
ddd93871d8 tilelink2: add an executable manager parameter 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
9bfd8c1cf5 TL2 WidthWidget (#258) 
* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses
 2016-09-08 10:38:38 -07:00
Wesley W. Terpstra
d2421654c4 tilelink2: refactor address into addr_hi on ABC and addr_lo on CD 
We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
 2016-09-06 23:46:44 -07:00
Wesley W. Terpstra
cb54df0a8a tilelink2: tie off unused channels 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
4746cf00ce tilelink2: move files to new uncore directory 2016-09-05 20:58:40 -07:00