riscv/rocket-chip
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1989 Commits

Author SHA1 Message Date
Wesley W. Terpstra
d89ee9d9d4 nodes: grab a name on construction 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
3656e975a1 diplomacy: ValName captures val bindings for Nodes 2017-09-22 14:38:47 -07:00
Henry Cook
81e136aa37 rocket: give l2 tlb a nice name 2017-09-21 18:13:39 -07:00
Henry Cook
30c8c8c517 Revert "try to give seqmems clearer names" 
This reverts commit 8db5bbbae0.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
 2017-09-21 18:02:32 -07:00
Henry Cook
e0b9f9213a make halt_and_catch_fire Optional 2017-09-21 14:58:47 -07:00
Henry Cook
28b635e721 tile: add halt_and_catch_fire signal 
for unrecoverable / fatal errors
 2017-09-21 14:58:47 -07:00
Henry Cook
a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Andrew Waterman
88c782cc70 Report D$ uncorrectable errors on C channel 2017-09-20 17:15:11 -07:00
Andrew Waterman
6bc20942b5 Don't cache TL error responses; report access exceptions 2017-09-20 17:01:08 -07:00
Andrew Waterman
9b828a2640 Only look at error signal on last beat 2017-09-20 15:15:21 -07:00
Andrew Waterman
026fa14bf8 Rename trace.addr -> iaddr 2017-09-20 14:32:41 -07:00
Andrew Waterman
5b2f458214 Merge branch 'master' into ma-fetch 2017-09-20 12:18:03 -07:00
Andrew Waterman
f1a506476b Merge pull request #994 from freechipsproject/beu 
Add L1 bus-error unit
 2017-09-20 12:17:08 -07:00
Andrew Waterman
f5bd639863 Don't write badaddr on misaligned fetch exceptions 
It's optional, and we were doing it wrong before, so just don't do it.
 2017-09-20 10:52:41 -07:00
Andrew Waterman
db57e943f3 Report TL errors into D$ 2017-09-20 00:05:07 -07:00
Andrew Waterman
aaad73f019 Add an intra-tile xbar 2017-09-20 00:05:07 -07:00
Andrew Waterman
afad25fceb Integrate L1 BusErrorUnit 2017-09-20 00:05:07 -07:00
Andrew Waterman
dbf599f6a1 Support SynchronizerShiftReg(sync = 0) 
This makes it easier to parameterize code where the synchronizer
might not always be needed.
 2017-09-20 00:05:07 -07:00
Andrew Waterman
79dab487fc Implement bus error unit 2017-09-20 00:05:07 -07:00
Andrew Waterman
ed18acaae0 Report D$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman
034ea722f4 Report I$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman
9a175b0fb1 Statically report error correction/detection capability from ECC codes 2017-09-20 00:05:07 -07:00
Andrew Waterman
4d6d6ff641 Add instruction-trace port 2017-09-19 22:59:57 -07:00
Andrew Waterman
acea94bcef Merge pull request #1001 from freechipsproject/address-decoder 
Address decoder "improvements"
 2017-09-19 22:38:53 -07:00
Jacob Chang
b4fc5104d4 Add cover property API that can be refined through Config PropertyLibrary (#998) 2017-09-19 19:26:54 -07:00
Henry Cook
57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems 
try to give seqmems clearer names for use with external tools
 2017-09-19 17:59:00 -07:00
Andrew Waterman
87b92cb206 Scan AddressDecoder bits left to right 
This heuristic is brittle but fixes deduplication in RocketTile.
 2017-09-19 17:47:24 -07:00
Andrew Waterman
72bd89a2af Add another AddressDecoder debug message 2017-09-19 17:47:17 -07:00
Andrew Waterman
fb2ad11347 Improve AddressDecoder optimization function 
This function is better 27% of the time but worse 6% of the time.
 2017-09-19 17:47:12 -07:00
Henry Cook
8db5bbbae0 try to give seqmems clearer names 2017-09-19 13:41:11 -07:00
Megan Wachs
826fc8ba61 Merge remote-tracking branch 'origin/master' into test_mode_reset 2017-09-18 09:50:27 -07:00
Andrew Waterman
d93d7b9fa4 Only merge stores that aren't yet pending 
This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed).  The following sequence manifests it, assuming t0
is 32-byte aligned:

    sw t0, 0(t0)
    sw t0, 16(t0)
    lw t1, 4(t0)
    lw t2, 4(t0)
 2017-09-17 15:01:07 -07:00
Megan Wachs
c85333f826 Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset 2017-09-17 13:51:46 -07:00
Megan Wachs
215e072e5c test_mode_reset: fix typos 2017-09-17 13:51:40 -07:00
Henry Cook
9b75dd7e5b Merge branch 'master' into test_mode_reset 2017-09-15 17:26:11 -07:00
Megan Wachs
641a8e7eab test_mode_reset: Correct some gender issues. Tie off signals in the test harness 2017-09-15 16:36:35 -07:00
Megan Wachs
6cda4504ac test_mode_reset: use a cleaner interface with bundles and options instead of individual signals 2017-09-15 12:30:39 -07:00
Megan Wachs
ffc514d1bc test_mode_reset: Add missing file 2017-09-14 13:17:37 -07:00
Megan Wachs
a0396b63e8 test_mode_reset: fix one bulk-connect gender issue 2017-09-14 13:16:13 -07:00
Megan Wachs
44edc5fdc3 test_mode_reset: Use simpler apply() method 2017-09-14 13:16:13 -07:00
Megan Wachs
82c00cb656 reset_catch: Allow Test Mode Overrides 2017-09-14 13:16:13 -07:00
Henry Cook
e50d14415e tilelink: more verbose requires 2017-09-13 11:25:42 -07:00
Henry Cook
56dae946b6 coreplex: MemoryBusParams.beatBytes also based on XLen 2017-09-13 11:25:42 -07:00
Henry Cook
b86f4b9bb7 config: use Field defaults over Config defaults 
Also rename some keys that had the same class name as their value's class name.
 2017-09-13 11:25:42 -07:00
Henry Cook
a7540d35b7 ports: use BigInts instead of Longs and the new x"..." context 2017-09-13 11:25:42 -07:00
Henry Cook
37c5af1c0d diplomacy: add x"..." string context 
Enables hex address literals containing underscores.
Converts them to BigInts.
 2017-09-13 11:25:42 -07:00
Henry Cook
063ca0ed4a Merge pull request #983 from freechipsproject/kill-paddrbits 
Remove global fields PAddrBits and ResetVectorBits
 2017-09-11 12:51:10 -07:00
Andrew Waterman
1f606d924f Don't perform in-place correction if there was a recent store (#988) 
Since the correction updates the entire word, the WAW hazard detection
logic is not sufficient to prevent overwriting a recent store.  So,
re-read the word after all pending stores have drained.
 2017-09-08 16:26:54 -07:00
Henry Cook
9c0bfbd500 tile: remove global Field ResetVectorBits 
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
 2017-09-08 14:50:59 -07:00
Henry Cook
3133c321b7 scratchpad: remove dependency on HasCoreParameters 2017-09-08 13:55:40 -07:00
Henry Cook
e46aeb7342 tile: remove PAddrBits in favor of SharedMemoryTLEdge 2017-09-08 13:53:36 -07:00
Wesley W. Terpstra
e7de7f3e82 Merge pull request #985 from freechipsproject/flop-interrupts 
Add Parameters to diplomatic edges
 2017-09-08 13:16:11 -07:00
Andrew Waterman
53dfc5e9be Remove overzealous assertion (#987) 
This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled.  However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.

This happens when resolving a tag ECC error during hit-under-miss.
 2017-09-07 18:17:56 -07:00
Wesley W. Terpstra
e723a3f42b MemoryBus: fanout the A for performance 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
6879f5bfb1 tilelink: Xbar now allows for fanout control 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
e831acba9c adapters: support bulk connections 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
06a244f9f9 diplomacy: rename {Left,Right}Star to refer to {Source,Sink}Cardinality 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
bef593c21a diplomacy: edges now capture their Parameters 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80ed27683e diplomacy: protect against API leakage 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1365c5f90c diplomacy: implement DisableMonitors scope 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
a450357744 tilelink: Monitor construction method is unconditional 
Whether or not a Monitor should be placed is decided by diplomacy.
 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
7a8364ef08 diplomacy: leverage new Parameters defaults 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
655a08f12e config: support default values for Field[T] keys 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
09d8d476c5 config: require Parameters keys to be Field[T] 
This has been good practice for ages. Enforce it.
 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
42f1ae27fc Xbar: use the IdentityModule to encourage wider fanout 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
5626cdd18f util: add the IdentityModule, useful to dedup wires 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1a87ed1193 coreplex: add externalSlaveBuffers configuration option 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
fd8a51a910 coreplex: rename externalBuffers to externalMasterBuffers 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
4911a7d44f tilelink Bus: toAsyncSlaves now supports BufferChains 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
040f7e1d49 tilelink: add Bus.toSyncSlaves for easy BufferChain attachment 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
d5c6494f59 tilelink: Bus.toRationalSlaves can have a BufferChain 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80965e8230 tilelink Buffer: use new :=? adapter API 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1b705f62f6 diplomacy: support :=? for unknown star inference 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
6bfea86dbf config: support p.lift(key) to optionally return a value 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
2d93262f71 RationalCrossing: use ShiftQueues 
These are faster and small don't cost much more.
 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
50d5d8c1fd ShiftQueue: added a helper object 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
3e3024c256 ShiftQueue: fix bug in !flow case 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
ed70b243bd plic: support a configurable number of interrupt register stages 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
9b55063de6 clint: support a configurable number of interrupt register stages 2017-09-07 16:03:34 -07:00
Megan Wachs
126d56b254 synchronizers: I learn how foldRight works 2017-09-07 10:48:27 -07:00
Megan Wachs
1da6cb85ab shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created. 2017-09-07 09:57:50 -07:00
Megan Wachs
dcafb5fea3 Merge remote-tracking branch 'origin/master' into async_reg 2017-09-06 11:07:19 -07:00
Megan Wachs
3c4b472f66 shift regs: remove some unnecessary primitives, and add some that actually are necessary 2017-09-06 10:37:59 -07:00
Jim Lawson
f1b7666d21 Jtagresettobool - add explicit toBool cast now required on reset. (#984) 
Add explicit toBool cast on reset, for chisel3 compatability
 2017-09-06 09:49:47 -07:00
Megan Wachs
777f052f95 regs: Add named/initial value ShiftRegister primitives so they are all in one place 2017-09-05 17:32:53 -07:00
Wesley W. Terpstra
b1cacc56ad SystemBus: restore correct order of FIFOFixer and Buffer 2017-09-05 16:41:39 -07:00
Wesley W. Terpstra
b74a419bfb FrontBus: FIFOFixer should not have a buffer between it and Xbar 2017-09-05 16:27:57 -07:00
Megan Wachs
e9e46db600 sync reg: Rename the file to reflect the more generic shift registers also in the file. 2017-09-05 15:54:25 -07:00
Megan Wachs
5df23c5514 Synchronizers: remove some newlines and unncessary gen's 2017-09-05 15:17:21 -07:00
Wesley W. Terpstra
e65f49b89a FrontBus: attach to splitter for cross-chip visibility 2017-09-05 15:03:41 -07:00
Wesley W. Terpstra
5886025b1a sbus => pbus: 2 buffers should already be enough 
There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.

Between them is only an AtomicAutomata.
That should be enough for most designs.
 2017-09-05 15:03:38 -07:00
Henry Cook
a902e15987 pbus: clarify that we are adding buffers when attaching to sbus 2017-09-05 15:03:38 -07:00
Henry Cook
8fc4d78c84 frontbus: provide fifofixer on the side of the front bus where masters connect 2017-09-05 15:03:38 -07:00
Megan Wachs
667d966410 TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming 2017-09-05 15:03:38 -07:00
Megan Wachs
94f06dc85c pbus: turn down overkill buffering between PBus and SBus 2017-09-05 15:03:38 -07:00
Megan Wachs
c353f68dc0 buses: name dummy buffers too 2017-09-05 15:03:38 -07:00
Henry Cook
3bde9506c6 coreplex: allow buffer chains on certain bus ports 2017-09-05 15:03:36 -07:00
Megan Wachs
57d0360c35 frontbus: Name the connection. 2017-08-30 18:07:34 -07:00
Megan Wachs
c99afe4c66 buses: Name all the things. 2017-08-30 17:31:42 -07:00
Henry Cook
32cb358c81 coreplex: include optional tile name for downstream name stabilization 2017-08-30 15:48:55 -07:00