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rocket-chip/src
Andrew Waterman d93d7b9fa4 Only merge stores that aren't yet pending
This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed).  The following sequence manifests it, assuming t0
is 32-byte aligned:

    sw t0, 0(t0)
    sw t0, 16(t0)
    lw t1, 4(t0)
    lw t2, 4(t0)
2017-09-17 15:01:07 -07:00
..
main/scala Only merge stores that aren't yet pending 2017-09-17 15:01:07 -07:00