riscv/rocket-chip
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07f0e6be943ecb10e3a939a6bcb1541132152877
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Author SHA1 Message Date
Howard Mao 51f128ec74 actually use backendBuffering in front of unwrapper/converter chain 2015-11-09 11:50:18 -08:00
Howard Mao cb0c2df051 update fpga-zynq 2015-11-05 10:50:13 -08:00
Howard Mao 42e7067400 bump uncore 2015-11-05 10:49:25 -08:00
Howard Mao bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Howard Mao fb501e75c0 fixes for sub-block TL requests in uncore 2015-11-05 10:48:32 -08:00
Howard Mao 7b252d8f89 get rid of now-unnecessary bits in MIF tag 2015-11-05 10:48:32 -08:00
Howard Mao ba5a6af05c correctly stripe data across memory channels in simulation 2015-11-05 10:48:32 -08:00
Howard Mao dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
Howard Mao 04d92dddbd add back decoupled NASTI connection at edge of RocketChip 2015-11-05 10:48:32 -08:00
Howard Mao 9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Howard Mao eb62ff6a50 add queues between Nasti -> TL converter and Nasti interconnect 2015-10-26 14:15:25 -07:00
Howard Mao f37938e4de implement MultiChannel routing 2015-10-26 14:15:25 -07:00
Howard Mao c3a7dcf0ab fix missing cde library dependencies in submodules 2015-10-23 15:05:19 -07:00
Howard Mao 21f342ad42 fix typo causing L2 cache configuration to fail 2015-10-21 13:37:33 -07:00
Howard Mao d5a75fd113 accidentally committed some code I didn't mean to in Rocket 2015-10-21 09:21:54 -07:00
Howard Mao 693a4ae00e fix some more memory system bugs 2015-10-20 23:29:59 -07:00
Howard Mao c311c9938e nitpicky declaration move 2015-10-20 21:10:54 -07:00
Howard Mao 4346111d2a fix remaining vsim harness typo 2015-10-19 20:20:14 -07:00
Howard Mao 896aa892d1 bump uncore for TL -> NASTI converter fix 2015-10-19 15:31:59 -07:00
Howard Mao c4117eb9a2 make sure TL parameters change properly throughout 
* Outermost TL parameters should have the width set to be the same as the
   MIF data width.
 * Broadcast Hub and Narrower, which use different sets of TL parameters
   should use the proper set of parameters at each interface
 2015-10-14 18:03:39 -07:00
Howard Mao a44e054c77 add support for different TileLink and MIF data widths 2015-10-13 12:46:23 -07:00
Howard Mao a76f0bf8fb fix involuntary release bug in rocket ProbeUnit 2015-09-30 17:26:48 -07:00
Howard Mao 353b00c8a1 revert some Chisel3-related changes and fix tlb bugs 2015-09-26 22:08:06 -07:00
Howard Mao c517d9f6e3 fix htif emulator constructor in vcs_main 2015-09-25 17:21:09 -07:00
Howard Mao 7b0167b92e make sure SCR and PCR data width matches xLen 2015-09-25 12:13:22 -07:00
Howard Mao 0e67d824b4 fix NASTI interconnect bug 2015-09-25 12:12:34 -07:00
Howard Mao 0d763524ef make sure conf address map scales with number of cores 2015-09-25 09:41:19 -07:00
Howard Mao 5e3f9115d3 make sure HTIF mem_mb doesn't exceed MMIOBase 2015-09-25 09:02:35 -07:00
Howard Mao c20ed350a0 even more Chisel3 compatability changes 2015-09-24 17:55:41 -07:00
Howard Mao 1c0111cc70 uncore merge commit 2015-09-24 17:10:45 -07:00
Howard Mao 8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:59:13 -07:00
Howard Mao 4a85c5a510 pull in hardfloat fixes 2015-09-24 16:58:49 -07:00
Howard Mao 38a9b23ce7 add a flag to only log and dump after a certain number of cycles 2015-09-22 10:32:31 -07:00
Howard Mao 4496e8d4e2 make sure htif_emulator properly sets memory size 2015-09-22 10:32:31 -07:00
Howard Mao 56ecdff52d Implement NASTI-based Mem/IO interconnect 2015-09-22 10:32:31 -07:00