riscv/rocket-chip
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1652 Commits

Author SHA1 Message Date
Colin Schmidt
675f183dd2 refactor ICache to be reusable by other frontends (#808) 
* refactor ICache to be reusable by other frontends

specifically one that would like to change the fetch width and number of
bytes in an instruction
 2017-06-20 08:21:01 -07:00
Andrew Waterman
a6d9884cc0 Improve integer mul/div 
- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
 2017-06-19 12:09:21 -07:00
Richard Xia
61c39da475 Check for rvc before declaring illegal instruction after an ebreak. 2017-06-16 10:49:36 -07:00
Wesley W. Terpstra
93d423d202 diplomacy: optimize IdRange.contains (#798) 
This should make an optimal circuit for a wider class of ranges.
 2017-06-15 15:56:14 -07:00
Shreesha Srinath
4059d9417f GeneratorUtils: support to elaborate a RawModule 2017-06-15 14:33:02 -07:00
Henry Cook
5368ea60fe Merge pull request #757 from freechipsproject/isp-port 
Inter-System-Port
 2017-06-15 13:07:19 -07:00
Wesley W. Terpstra
1f8c4ba4ca CoreplexNetwork: don't force a buffer on the coherence manager 
Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
 2017-06-14 14:27:23 -07:00
Wesley W. Terpstra
4a15d47061 diplomacy: BufferParams can now directly create a Queue 2017-06-14 13:47:37 -07:00
Wesley W. Terpstra
b4b165112c PeripheryErrorSlave: do not put a TLMonitor between the fragmenter and slave 
This edge has the largest number of source bits by far. Let's just exclude it.
 2017-06-13 16:59:29 -07:00
Wesley W. Terpstra
94f85e8bc8 tilelink2: TLMonitor will not create giant wires 2017-06-13 16:58:22 -07:00
Colin Schmidt
8264c0a77e add a debug print for xbar id mappings 2017-06-13 16:58:21 -07:00
Henry Cook
9bbde9767c rocketchip: top-level systems are now multi-IO modules 
Cake pattern only 2 layers instead of 3.
Standardized naming convention.
Comments for periphery mix-ins.
Testharnesses use new periphery helper methods.
 2017-06-13 13:55:45 -07:00
Henry Cook
2e8a40a23f diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules 
And add a MonitorBase class to be connect's return type.
 2017-06-13 13:55:27 -07:00
Andrew Waterman
76af15a6ff Fix FPU control bug for div/sqrt 
I was examining a WB-stage control signal instead of a MEM-stage control
signal.  I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
 2017-06-09 15:51:06 -07:00
Andrew Waterman
8552c77972 Fix I$ reset regression FU-357 
Can't rely on s2 TLB response, so mask using s2_valid.
 2017-06-09 00:48:24 -07:00
Andrew Waterman
5a4daebbcc minNum -> minimumNumber (#766) 2017-06-08 11:12:52 -07:00
Andrew Waterman
8cb250cfe6 Fix FMUL sign, again (#789) 2017-06-08 01:50:00 -07:00
Leway Colin
60c896b48c Typo: is should be if ? (#786) 
Typo: is should be if ?
 2017-06-07 10:40:13 -07:00
Andrew Waterman
d45fc0d670 Merge pull request #785 from freechipsproject/fmul-fix 
Fix FMUL sign of zero
 2017-06-06 00:46:03 -07:00
Andrew Waterman
07ad9203ff Fix FMUL sign of zero 2017-06-05 17:35:42 -07:00
Megan Wachs
8d2e9a8631 Merge remote-tracking branch 'origin/master' into plusarg_docstring 2017-06-05 17:23:44 -07:00
Wesley W. Terpstra
87a5665e43 axi4: only block writes if SAME master has outstanding reads (#782) 
* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
 2017-06-05 16:54:00 -07:00
Megan Wachs
7afd5e6070 remove unnecessary whitespace. Fix grammar. 2017-06-05 16:18:57 -07:00
Megan Wachs
8440c4b1c4 plusarg_reader : Add the ability to add a documentation string. 2017-06-05 16:16:52 -07:00
solomatnikov
274d908d98 Changed TLXbar arbitration policy to roundRobin (#781) 2017-06-05 10:20:28 -07:00
Andrew Waterman
16ecbdd5b2 Reduce fanout on critical I$ miss signal 2017-06-02 20:45:50 -07:00
Andrew Waterman
27b143013f Improve ITLB QoR 
- No need to check cacheability
- Remove a gate delay from PMP path
 2017-06-02 20:45:50 -07:00
Andrew Waterman
0ffb2c8baf Simplify and improve QoR of ShiftQueue 2017-06-02 20:44:52 -07:00
Andrew Waterman
8229bdee03 Remove FP unboxing from FMA critical path 2017-06-02 20:44:52 -07:00
Andrew Waterman
7504b47bbe Improve code quality in FP->FP and Int->FP units 2017-06-02 20:44:52 -07:00
Andrew Waterman
84c4ae775f Improve QoR for FP->Int conversions 2017-06-02 20:44:52 -07:00
Andrew Waterman
07968df183 Refactor FP Classify 2017-06-02 20:44:52 -07:00
Andrew Waterman
6ecd58a977 Incorporate new div/sqrt unit 2017-06-02 20:44:15 -07:00
Wesley W. Terpstra
b1917e7915 coreplex: add an ISPPort trait to add cross-connect points 2017-06-02 20:43:23 -07:00
Wesley W. Terpstra
81d372137a coreplex: unconditionally insert a Splitter between tiles and l1tol2 2017-06-02 20:43:21 -07:00
Wesley W. Terpstra
d002cec6ac NodeNumberer: add an adapter to map inter-chip fabrics 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
5a2a6b0386 diplomacy: add a CustomNode type that allows direct overload of methods 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
fed1f53afa tilelink2: add a TLSplitter to be used for the ISP port 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
a4bf678954 tilelink2: fix latent Xbar truncation bug 
This was introduced when we switched to HeterogeneousBag for diplomatic IO.
It seems a lucky coincidence that nothing has run into this yet!
 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
ce12a64f4b tilelink2: support SplitterNodes 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
de39af7f65 tilelink2: make some Xbar methods reusable 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
0a2a93c27d diplomacy: add the new Splitter node type 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
c695237050 diplomacy: make :=* and :*= resolution more flexible 2017-06-02 20:42:16 -07:00
edwardcwang
cdbf67be68 Add a note to wire up jtag_mfr_id (#778) 
Close #774
 2017-06-02 18:53:14 -07:00
Wesley W. Terpstra
e0741a2097 axi4: don't map unused masters into TL source ID space 2017-06-02 16:30:16 -07:00
Wesley W. Terpstra
80c63c0da6 rocket: include hartid in cache master names 2017-06-02 15:52:23 -07:00
Wesley W. Terpstra
d25ad10592 diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Wesley W. Terpstra
475ac93cdf coreplex: print memory map using DTS, also write a JSON for it 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
ae8734da05 diplomacy: report cacheability in ResourceAddress 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
985d9750e6 tilelink2: Xbar QoR improvement 2017-06-02 14:27:40 -07:00