From ff1f0170dc5eb131dfc30aa1e00f3f35b6df88ca Mon Sep 17 00:00:00 2001 From: Shreesha Srinath Date: Fri, 16 Jun 2017 22:47:12 -0700 Subject: [PATCH] changing SystemVerilog params to Verilog style (#801) vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters --- vsrc/plusarg_reader.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vsrc/plusarg_reader.v b/vsrc/plusarg_reader.v index 7a7bacc9..4ac275a4 100644 --- a/vsrc/plusarg_reader.v +++ b/vsrc/plusarg_reader.v @@ -2,7 +2,7 @@ // No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment), // but Incisive demands them. These default values should never be used. -module plusarg_reader #(string FORMAT="borked=%d", int DEFAULT=0) ( +module plusarg_reader #(FORMAT="borked=%d", DEFAULT=0) ( output [31:0] out );