riscv/rocket-chip
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Merge pull request #311 from ucb-bar/rom-executable

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Rom executable
This commit is contained in:
Wesley W. Terpstra 2016-09-17 01:28:52 -07:00 committed by GitHub
commit fd3ac4653c
4 changed files with 16 additions and 5 deletions
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7
src/main/scala/rocketchip/Top.scala
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@ -76,7 +76,12 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
val name = entry.name
val start = entry.region.start
val end = entry.region.start + entry.region.size - 1
println(f"\t$name%s $start%x - $end%x")
val prot = entry.region.attr.prot
val protStr = (if ((prot & AddrMapProt.R) > 0) "R" else "") +
(if ((prot & AddrMapProt.W) > 0) "W" else "") +
(if ((prot & AddrMapProt.X) > 0) "X" else "")
val cacheable = if (entry.region.attr.cacheable) " [C]" else ""
println(f"\t$name%s $start%x - $end%x, $protStr$cacheable")
}
println("Generated Configuration String")

7
src/main/scala/rocketchip/Utils.scala
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@ -66,10 +66,15 @@ object GenerateGlobalAddrMap {
}
lazy val tl2Devices = peripheryManagers.map { manager =>
val cacheable = manager.regionType match {
case RegionType.CACHED => true
case RegionType.TRACKED => true
case _ => false
}
val attr = MemAttr(
(if (manager.supportsGet) AddrMapProt.R else 0) |
(if (manager.supportsPutFull) AddrMapProt.W else 0) |
(if (manager.executable) AddrMapProt.X else 0))
(if (manager.executable) AddrMapProt.X else 0), cacheable)
val multi = manager.address.size > 1
manager.address.zipWithIndex.map { case (address, i) =>
require (!address.strided) // TL1 can't do this

3
src/main/scala/uncore/devices/Rom.scala
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@ -8,11 +8,12 @@ import uncore.tilelink2._
import uncore.util._
import cde.{Parameters, Field}
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], beatBytes: Int = 4) extends LazyModule
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
{
val node = TLManagerNode(beatBytes, TLManagerParameters(
address = List(AddressSet(base, size-1)),
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
fifoId = Some(0)))

4
src/main/scala/uncore/tilelink2/SRAM.scala
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@ -4,12 +4,12 @@ package uncore.tilelink2
import Chisel._
class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
{
val node = TLManagerNode(beatBytes, TLManagerParameters(
address = List(address),
regionType = RegionType.UNCACHED,
executable = true,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),