diff --git a/src/main/scala/rocketchip/Top.scala b/src/main/scala/rocketchip/Top.scala
index 6ea9069c..ef4a98b4 100644
--- a/src/main/scala/rocketchip/Top.scala
+++ b/src/main/scala/rocketchip/Top.scala
@@ -76,7 +76,12 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
     val name = entry.name
     val start = entry.region.start
     val end = entry.region.start + entry.region.size - 1
-    println(f"\t$name%s $start%x - $end%x")
+    val prot = entry.region.attr.prot
+    val protStr = (if ((prot & AddrMapProt.R) > 0) "R" else "") +
+                  (if ((prot & AddrMapProt.W) > 0) "W" else "") +
+                  (if ((prot & AddrMapProt.X) > 0) "X" else "")
+    val cacheable = if (entry.region.attr.cacheable) " [C]" else ""
+    println(f"\t$name%s $start%x - $end%x, $protStr$cacheable")
   }
 
   println("Generated Configuration String")
diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala
index 8f27cc1b..9dec5cb3 100644
--- a/src/main/scala/rocketchip/Utils.scala
+++ b/src/main/scala/rocketchip/Utils.scala
@@ -66,10 +66,15 @@ object GenerateGlobalAddrMap {
     }
 
     lazy val tl2Devices = peripheryManagers.map { manager =>
+      val cacheable = manager.regionType match {
+        case RegionType.CACHED   => true
+        case RegionType.TRACKED  => true
+        case _ => false
+      }
       val attr = MemAttr(
         (if (manager.supportsGet)     AddrMapProt.R else 0) |
         (if (manager.supportsPutFull) AddrMapProt.W else 0) |
-        (if (manager.executable)      AddrMapProt.X else 0))
+        (if (manager.executable)      AddrMapProt.X else 0), cacheable)
       val multi = manager.address.size > 1
       manager.address.zipWithIndex.map { case (address, i) =>
         require (!address.strided) // TL1 can't do this
diff --git a/src/main/scala/uncore/devices/Rom.scala b/src/main/scala/uncore/devices/Rom.scala
index 8e31cbe5..2986f85c 100644
--- a/src/main/scala/uncore/devices/Rom.scala
+++ b/src/main/scala/uncore/devices/Rom.scala
@@ -8,11 +8,12 @@ import uncore.tilelink2._
 import uncore.util._
 import cde.{Parameters, Field}
 
-class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], beatBytes: Int = 4) extends LazyModule
+class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
 {
   val node = TLManagerNode(beatBytes, TLManagerParameters(
     address     = List(AddressSet(base, size-1)),
     regionType  = RegionType.UNCACHED,
+    executable  = executable,
     supportsGet = TransferSizes(1, beatBytes),
     fifoId      = Some(0)))
 
diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala
index 2970eb78..84a775f2 100644
--- a/src/main/scala/uncore/tilelink2/SRAM.scala
+++ b/src/main/scala/uncore/tilelink2/SRAM.scala
@@ -4,12 +4,12 @@ package uncore.tilelink2
 
 import Chisel._
 
-class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
+class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
 {
   val node = TLManagerNode(beatBytes, TLManagerParameters(
     address            = List(address),
     regionType         = RegionType.UNCACHED,
-    executable         = true,
+    executable         = executable,
     supportsGet        = TransferSizes(1, beatBytes),
     supportsPutPartial = TransferSizes(1, beatBytes),
     supportsPutFull    = TransferSizes(1, beatBytes),