From e4b56b5d0e2320ac7d2261d0fe60ec1d9fdf09fd Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 15 Mar 2014 15:31:04 -0700 Subject: [PATCH] generate verilog for rekall --- project/build.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/project/build.scala b/project/build.scala index a6f98650..877c66a4 100644 --- a/project/build.scala +++ b/project/build.scala @@ -31,7 +31,8 @@ object BuildSettings extends Build { lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore) lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket) - lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha) + lazy val rekall = Project("rekall", file("rekall"), settings = buildSettings) dependsOn(chisel) + lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha, rekall) val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code") val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")