riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

debug: add clock crossing primitives

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-07-18 14:29:13 -07:00 committed by Howard Mao
parent e406d1bd73
commit fa8317fec1
1 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
uncore/src/main/scala/devices/Debug.scala
View File

@ -983,3 +983,21 @@ class DebugModule ()(implicit val p:cde.Parameters)
io.fullreset := CONTROLReg.fullreset io.fullreset := CONTROLReg.fullreset
} }
object AsyncDebugBusFrom { // OutsideClockDomain
def apply(from_clock: Clock, from_reset: Bool, source: DebugBusIO, depth: Int = 0, sync: Int = 2)(implicit p: Parameters): DebugBusIO = {
val sink = Wire(new DebugBusIO)
sink.req <> AsyncDecoupledFrom(from_clock, from_reset, source.req)
source.resp <> AsyncDecoupledTo(from_clock, from_reset, sink.resp)
sink
}
}
object AsyncDebugBusTo { // OutsideClockDomain
def apply(to_clock: Clock, to_reset: Bool, source: DebugBusIO, depth: Int = 0, sync: Int = 2)(implicit p: Parameters): DebugBusIO = {
val sink = Wire(new DebugBusIO)
sink.req <> AsyncDecoupledTo(to_clock, to_reset, source.req)
source.resp <> AsyncDecoupledFrom(to_clock, to_reset, sink.resp)
sink
}
}