From fa8317fec1c3ad50449a80bd5e3d9179f021439c Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Mon, 18 Jul 2016 14:29:13 -0700
Subject: [PATCH] debug: add clock crossing primitives

---
 uncore/src/main/scala/devices/Debug.scala | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/uncore/src/main/scala/devices/Debug.scala b/uncore/src/main/scala/devices/Debug.scala
index 9513e171..dc9468b1 100644
--- a/uncore/src/main/scala/devices/Debug.scala
+++ b/uncore/src/main/scala/devices/Debug.scala
@@ -983,3 +983,21 @@ class DebugModule ()(implicit val p:cde.Parameters)
   io.fullreset := CONTROLReg.fullreset
 
 }
+
+object AsyncDebugBusFrom { // OutsideClockDomain
+  def apply(from_clock: Clock, from_reset: Bool, source: DebugBusIO, depth: Int = 0, sync: Int = 2)(implicit p: Parameters): DebugBusIO = {
+    val sink = Wire(new DebugBusIO)
+    sink.req <> AsyncDecoupledFrom(from_clock, from_reset, source.req)
+    source.resp <> AsyncDecoupledTo(from_clock, from_reset, sink.resp)
+    sink
+  }
+}
+
+object AsyncDebugBusTo { // OutsideClockDomain
+  def apply(to_clock: Clock, to_reset: Bool, source: DebugBusIO, depth: Int = 0, sync: Int = 2)(implicit p: Parameters): DebugBusIO = {
+    val sink = Wire(new DebugBusIO)
+    sink.req <> AsyncDecoupledTo(to_clock, to_reset, source.req)
+    source.resp <> AsyncDecoupledFrom(to_clock, to_reset, sink.resp)
+    sink
+  }
+}