riscv/rocket-chip
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Rename PRCICoreIO to PRCITileIO

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This commit is contained in:
Andrew Waterman 2016-05-02 18:08:01 -07:00
parent 000e20f937
commit f784f4da93
3 changed files with 3 additions and 3 deletions
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2
rocket/src/main/scala/csr.scala
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@ -76,7 +76,7 @@ object CSR
} }
class CSRFileIO(implicit p: Parameters) extends CoreBundle { class CSRFileIO(implicit p: Parameters) extends CoreBundle {
val prci = new PRCICoreIO().flip val prci = new PRCITileIO().flip
val rw = new Bundle { val rw = new Bundle {
val addr = UInt(INPUT, CSR.ADDRSZ) val addr = UInt(INPUT, CSR.ADDRSZ)
val cmd = Bits(INPUT, CSR.SZ) val cmd = Bits(INPUT, CSR.SZ)

2
rocket/src/main/scala/rocket.scala
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@ -110,7 +110,7 @@ object ImmGen {
class Rocket(implicit p: Parameters) extends CoreModule()(p) { class Rocket(implicit p: Parameters) extends CoreModule()(p) {
val io = new Bundle { val io = new Bundle {
val prci = new PRCICoreIO().flip val prci = new PRCITileIO().flip
val imem = new FrontendIO()(p.alterPartial({case CacheName => "L1I" })) val imem = new FrontendIO()(p.alterPartial({case CacheName => "L1I" }))
val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" })) val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
val ptw = new DatapathPTWIO().flip val ptw = new DatapathPTWIO().flip

2
rocket/src/main/scala/tile.scala
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@ -31,7 +31,7 @@ abstract class Tile(resetSignal: Bool = null)
val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO) val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO) val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
val host = new HtifIO // Unused, but temporarily extant for zscale/groundtest val host = new HtifIO // Unused, but temporarily extant for zscale/groundtest
val prci = new PRCICoreIO().flip val prci = new PRCITileIO().flip
val dma = new DmaIO val dma = new DmaIO
} }
} }