diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index b9ac2b65..d91332e7 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -76,7 +76,7 @@ object CSR
 }
 
 class CSRFileIO(implicit p: Parameters) extends CoreBundle {
-  val prci = new PRCICoreIO().flip
+  val prci = new PRCITileIO().flip
   val rw = new Bundle {
     val addr = UInt(INPUT, CSR.ADDRSZ)
     val cmd = Bits(INPUT, CSR.SZ)
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 05fcfbcb..97938ee0 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -110,7 +110,7 @@ object ImmGen {
 
 class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   val io = new Bundle {
-    val prci = new PRCICoreIO().flip
+    val prci = new PRCITileIO().flip
     val imem  = new FrontendIO()(p.alterPartial({case CacheName => "L1I" }))
     val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
     val ptw = new DatapathPTWIO().flip
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index e21d81ae..4312fc47 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -31,7 +31,7 @@ abstract class Tile(resetSignal: Bool = null)
     val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
     val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
     val host = new HtifIO // Unused, but temporarily extant for zscale/groundtest
-    val prci = new PRCICoreIO().flip
+    val prci = new PRCITileIO().flip
     val dma = new DmaIO
   }
 }