Rename PRCICoreIO to PRCITileIO
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@ -31,7 +31,7 @@ abstract class Tile(resetSignal: Bool = null)
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val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
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val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
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val host = new HtifIO // Unused, but temporarily extant for zscale/groundtest
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val prci = new PRCICoreIO().flip
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val prci = new PRCITileIO().flip
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val dma = new DmaIO
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}
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}
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