riscv/rocket-chip
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rocket: connect uncrossed output interrupts

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This commit is contained in:
Henry Cook 2017-09-27 12:53:19 -07:00
parent 1fda05970a
commit f48bf2ac2f
1 changed files with 2 additions and 0 deletions
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src/main/scala/tile/RocketTile.scala
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@ -213,6 +213,8 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
def outputInterruptXingLatency: Int
intOutputNode.foreach { _ := rocket.intOutputNode.get }
lazy val module = new LazyModuleImp(this) {
val io = new CoreBundle
with HasExternallyDrivenTileConstants