From f48bf2ac2f36990e876ba15b0db8f3226901d2ef Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Wed, 27 Sep 2017 12:53:19 -0700
Subject: [PATCH] rocket: connect uncrossed output interrupts

---
 src/main/scala/tile/RocketTile.scala | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index 0e83eb3c..376a2620 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -213,6 +213,8 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
 
   def outputInterruptXingLatency: Int
 
+  intOutputNode.foreach { _ := rocket.intOutputNode.get }
+
   lazy val module = new LazyModuleImp(this) {
     val io = new CoreBundle
         with HasExternallyDrivenTileConstants