decouple all interfaces between tile and top

also, add an "incoherent" bit to tilelink to indicate no probes needed

rocket/src/main/scala/arbiter.scala

@@ -7,7 +7,7 @@ import Constants._;
 class ioUncachedRequestor extends Bundle {
   val xact_init      = (new FIFOIO) { new TransactionInit }
   val xact_abort     = (new FIFOIO) { new TransactionAbort }.flip
-  val xact_rep       = (new PipeIO)      { new TransactionReply }.flip
+  val xact_rep       = (new FIFOIO)      { new TransactionReply }.flip
   val xact_finish    = (new FIFOIO) { new TransactionFinish }
 }
 
@@ -74,4 +74,5 @@ class rocketMemArbiter(n: Int) extends Component {
   }
 
   io.mem.xact_abort.ready := Bool(true)
+  io.mem.xact_rep.ready := Bool(true)
 }

rocket/src/main/scala/cpu.scala

@@ -13,7 +13,7 @@ class ioRocket extends Bundle()
   val dmem    = new ioHellaCache
 }
 
-class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
+class rocketProc extends Component
 {
   val io    = new ioRocket
    

rocket/src/main/scala/htif.scala

@@ -105,6 +105,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
     mem_gxid := io.mem.xact_rep.bits.global_xact_id
     mem_needs_ack := io.mem.xact_rep.bits.require_ack  
   }
+  io.mem.xact_rep.ready := Bool(true)
   when (io.mem.xact_abort.valid) { mem_nacked := Bool(true) }
 
   val state_rx :: state_pcr :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(8) { UFix() }
@@ -183,13 +184,10 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
   io.mem.xact_init_data.bits.data := mem_req_data
   io.mem.xact_finish.valid := (state === state_mem_finish) && mem_needs_ack
   io.mem.xact_finish.bits.global_xact_id := mem_gxid
-
+  io.mem.probe_req.ready := Bool(false)
-  val probe_q = (new queue(1)) { new ProbeReply }
+  io.mem.probe_rep.valid := Bool(false)
-  probe_q.io.enq.valid := io.mem.probe_req.valid
-  io.mem.probe_req.ready := probe_q.io.enq.ready
-  probe_q.io.enq.bits := co.newProbeReply(io.mem.probe_req.bits, co.newStateOnFlush())
-  io.mem.probe_rep <> probe_q.io.deq
   io.mem.probe_rep_data.valid := Bool(false)
+  io.mem.incoherent := Bool(true)
 
   pcr_done := Bool(false)
   val pcr_mux = (new Mux1H(ncores)) { Bits(width = 64) }

rocket/src/main/scala/llc.scala

@@ -107,7 +107,7 @@ class LLCMSHRFile(sets: Int, ways: Int, outstanding: Int) extends Component
       val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
       val way = UFix(width = log2Up(ways))
     } }
-    val mem = new ioMem
+    val mem = new ioMemPipe
     val mem_resp_set = UFix(OUTPUT, log2Up(sets))
     val mem_resp_way = UFix(OUTPUT, log2Up(ways))
   }
@@ -194,7 +194,7 @@ class LLCWriteback(requestors: Int) extends Component
   val io = new Bundle {
     val req = Vec(requestors) { (new FIFOIO) { UFix(width = PADDR_BITS - OFFSET_BITS) }.flip }
     val data = Vec(requestors) { (new FIFOIO) { new MemData }.flip }
-    val mem = new ioMem
+    val mem = new ioMemPipe
   }
 
   val valid = Reg(resetVal = Bool(false))
@@ -245,7 +245,7 @@ class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
     val req_data = (new FIFOIO) { new MemData }.flip
     val writeback = (new FIFOIO) { UFix(width = PADDR_BITS - OFFSET_BITS) }
     val writeback_data = (new FIFOIO) { new MemData }
-    val resp = (new PipeIO) { new MemResp }
+    val resp = (new FIFOIO) { new MemResp }
     val mem_resp = (new PipeIO) { new MemResp }.flip
     val mem_resp_set = UFix(INPUT, log2Up(sets))
     val mem_resp_way = UFix(INPUT, log2Up(ways))
@@ -298,7 +298,7 @@ class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
   io.writeback.valid := io.req.valid && io.req.ready && io.req.bits.isWriteback
   io.writeback.bits := io.req.bits.addr
 
-  q.io.deq.ready := Mux(q.io.deq.bits.isWriteback, io.writeback_data.ready, Bool(true))
+  q.io.deq.ready := Mux(q.io.deq.bits.isWriteback, io.writeback_data.ready, io.resp.ready)
   io.resp.valid := q.io.deq.valid && !q.io.deq.bits.isWriteback
   io.resp.bits := q.io.deq.bits
   io.writeback_data.valid := q.io.deq.valid && q.io.deq.bits.isWriteback
@@ -309,7 +309,7 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[Bits], da
 {
   val io = new Bundle {
     val cpu = new ioMem().flip
-    val mem = new ioMem
+    val mem = new ioMemPipe
   }
 
   val tagWidth = PADDR_BITS - OFFSET_BITS - log2Up(sets)

rocket/src/main/scala/queues.scala

@@ -73,7 +73,9 @@ object Queue
 {
   def apply[T <: Data](enq: FIFOIO[T], entries: Int = 2, pipe: Boolean = false) = {
     val q = (new queue(entries, pipe)) { enq.bits.clone }
-    q.io.enq <> enq
+    q.io.enq.valid := enq.valid // not using <> so that override is allowed
+    q.io.enq.bits := enq.bits
+    enq.ready := q.io.enq.ready
     q.io.deq
   }
 }

rocket/src/main/scala/tile.scala

@@ -4,14 +4,14 @@ import Chisel._
 import Node._
 import Constants._
 
-class Tile(co: CoherencePolicyWithUncached) extends Component
+class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Component(resetSignal)
 {
   val io = new Bundle {
     val tilelink = new ioTileLink
     val host = new ioHTIF
   }
   
-  val cpu       = new rocketProc(resetSignal = io.host.reset)
+  val cpu       = new rocketProc
   val icache    = new rocketICache(128, 4, co) // 128 sets x 4 ways (32KB)
   val dcache    = new HellaCache(co)
 
@@ -19,14 +19,14 @@ class Tile(co: CoherencePolicyWithUncached) extends Component
   arbiter.io.requestor(0) <> dcache.io.mem
   arbiter.io.requestor(1) <> icache.io.mem
 
-  io.tilelink.xact_init <> Queue(arbiter.io.mem.xact_init)
+  io.tilelink.xact_init <> arbiter.io.mem.xact_init
-  io.tilelink.xact_init_data <> Queue(dcache.io.mem.xact_init_data)
+  io.tilelink.xact_init_data <> dcache.io.mem.xact_init_data
-  arbiter.io.mem.xact_abort <> Queue(io.tilelink.xact_abort)
+  arbiter.io.mem.xact_abort <> io.tilelink.xact_abort
-  arbiter.io.mem.xact_rep <> Pipe(io.tilelink.xact_rep)
+  arbiter.io.mem.xact_rep <> io.tilelink.xact_rep
-  io.tilelink.xact_finish <> Queue(arbiter.io.mem.xact_finish)
+  io.tilelink.xact_finish <> arbiter.io.mem.xact_finish
-  dcache.io.mem.probe_req <> Queue(io.tilelink.probe_req)
+  dcache.io.mem.probe_req <> io.tilelink.probe_req
-  io.tilelink.probe_rep <> Queue(dcache.io.mem.probe_rep, 1)
+  io.tilelink.probe_rep <> dcache.io.mem.probe_rep
-  io.tilelink.probe_rep_data <> Queue(dcache.io.mem.probe_rep_data)
+  io.tilelink.probe_rep_data <> dcache.io.mem.probe_rep_data
 
   if (HAVE_VEC)
   {

rocket/src/main/scala/top.scala

@@ -12,7 +12,7 @@ class ioTop(htif_width: Int) extends Bundle  {
   val mem_backup = new ioMemSerialized
   val mem_backup_en = Bool(INPUT)
   val mem_backup_clk = Bool(OUTPUT)
-  val mem     = new ioMem
+  val mem     = new ioMemPipe
 }
 
 class Top extends Component
@@ -79,9 +79,18 @@ class Top extends Component
 
   var error_mode = Bool(false)
   for (i <- 0 until NTILES) {
-    val tile = new Tile(co)
+    val tile = new Tile(co, resetSignal = htif.io.cpu(i).reset)
+    val h = hub.io.tiles(i)
     tile.io.host <> htif.io.cpu(i)
-    hub.io.tiles(i) <> tile.io.tilelink
+    h.xact_init <> Queue(tile.io.tilelink.xact_init)
+    h.xact_init_data <> Queue(tile.io.tilelink.xact_init_data)
+    tile.io.tilelink.xact_abort <> Queue(h.xact_abort)
+    tile.io.tilelink.xact_rep <> Queue(h.xact_rep, 1, pipe = true)
+    h.xact_finish <> Queue(tile.io.tilelink.xact_finish)
+    tile.io.tilelink.probe_req <> Queue(h.probe_req)
+    h.probe_rep <> Queue(tile.io.tilelink.probe_rep, 1)
+    h.probe_rep_data <> Queue(tile.io.tilelink.probe_rep_data)
+    h.incoherent := htif.io.cpu(i).reset
     error_mode = error_mode || tile.io.host.debug.error_mode
   }
   io.debug.error_mode := error_mode

rocket/src/main/scala/uncore.scala

@@ -20,6 +20,13 @@ class MemResp () extends MemData
 }
 
 class ioMem() extends Bundle
+{
+  val req_cmd  = (new FIFOIO) { new MemReqCmd() }
+  val req_data = (new FIFOIO) { new MemData() }
+  val resp     = (new FIFOIO) { new MemResp() }.flip
+}
+
+class ioMemPipe() extends Bundle
 {
   val req_cmd  = (new FIFOIO) { new MemReqCmd() }
   val req_data = (new FIFOIO) { new MemData() }
@@ -46,8 +53,9 @@ class ioTileLink extends Bundle {
   val probe_req      = (new FIFOIO) { new ProbeRequest }.flip
   val probe_rep      = (new FIFOIO) { new ProbeReply }
   val probe_rep_data = (new FIFOIO) { new ProbeReplyData }
-  val xact_rep       = (new PipeIO)      { new TransactionReply }.flip
+  val xact_rep       = (new FIFOIO) { new TransactionReply }.flip
   val xact_finish    = (new FIFOIO) { new TransactionFinish }
+  val incoherent     = Bool(OUTPUT)
 }
 
 class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
@@ -58,6 +66,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
     val xact_finish     = Bool(INPUT)
     val p_rep_cnt_dec   = Bits(INPUT, ntiles)
     val p_req_cnt_inc   = Bits(INPUT, ntiles)
+    val tile_incoherent = Bits(INPUT, ntiles)
     val p_rep_data      = (new PipeIO) { new ProbeReplyData }.flip
     val x_init_data     = (new PipeIO) { new TransactionInitData }.flip
     val sent_x_rep_ack  = Bool(INPUT)
@@ -169,7 +178,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
         tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
         x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.xact_init)
         x_needs_read := co.needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
-        val p_req_initial_flags = ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only
+        val p_req_initial_flags = ~(io.tile_incoherent | UFixToOH(io.alloc_req.bits.tile_id)) //TODO: Broadcast only
         p_req_flags := p_req_initial_flags(ntiles-1,0)
         mem_cnt := UFix(0)
         p_w_mem_cmd_sent := Bool(false)
@@ -310,6 +319,7 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
     t.p_data.valid        := p_data_valid_arr(i)
     t.p_rep_cnt_dec       := p_rep_cnt_dec_arr(i).toBits
     t.p_req_cnt_inc       := p_req_cnt_inc_arr(i).toBits
+    t.tile_incoherent     := (Vec(io.tiles.map(_.incoherent)) { Bool() }).toBits
     t.sent_x_rep_ack      := sent_x_rep_ack_arr(i)
     do_free_arr(i)        := Bool(false)
     sent_x_rep_ack_arr(i) := Bool(false)
@@ -360,8 +370,7 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
       }
     }
   }
-  // If there were a ready signal due to e.g. intervening network use:
+  io.mem.resp.ready  := io.tiles(init_tile_id_arr(mem_idx)).xact_rep.ready
-  //io.mem.resp.ready  := io.tiles(init_tile_id_arr.read(mem_idx)).xact_rep.ready
 
   // Create an arbiter for the one memory port
   // We have to arbitrate between the different trackers' memory requests