115 lines
2.9 KiB
Scala
115 lines
2.9 KiB
Scala
package rocket
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import Chisel._
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import Node._;
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class ioQueue[T <: Data](entries: Int, flushable: Boolean)(data: => T) extends Bundle
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{
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val flush = if (flushable) Bool(INPUT) else null
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val enq = new FIFOIO()(data).flip
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val deq = new FIFOIO()(data)
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val count = UFix(OUTPUT, log2Up(entries+1))
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}
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class queue[T <: Data](val entries: Int, pipe: Boolean = false, flushable: Boolean = false)(data: => T) extends Component
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{
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val io = new ioQueue(entries, flushable)(data)
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val do_enq = io.enq.ready && io.enq.valid
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val do_deq = io.deq.ready && io.deq.valid
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var enq_ptr = UFix(0)
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var deq_ptr = UFix(0)
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val pow2 = (entries & (entries-1)) == 0
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if (entries > 1)
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{
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enq_ptr = Reg(resetVal = UFix(0, log2Up(entries)))
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deq_ptr = Reg(resetVal = UFix(0, log2Up(entries)))
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var enq_next = enq_ptr + UFix(1)
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var deq_next = deq_ptr + UFix(1)
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if (!pow2) {
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enq_next = Mux(enq_ptr === UFix(entries-1), UFix(0), enq_next)
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deq_next = Mux(deq_ptr === UFix(entries-1), UFix(0), deq_next)
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}
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when (do_deq) { deq_ptr := deq_next }
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when (do_enq) { enq_ptr := enq_next }
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if (flushable) {
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when (io.flush) {
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deq_ptr := UFix(0)
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enq_ptr := UFix(0)
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}
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}
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}
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val maybe_full = Reg(resetVal = Bool(false))
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when (do_enq != do_deq) {
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maybe_full := do_enq
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}
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if (flushable) {
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when (io.flush) {
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maybe_full := Bool(false)
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}
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}
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val ram = Mem(entries) { data }
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when (do_enq) { ram(enq_ptr) := io.enq.bits }
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val ptr_match = enq_ptr === deq_ptr
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io.deq.valid := maybe_full || !ptr_match
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io.enq.ready := !maybe_full || !ptr_match || (if (pipe) io.deq.ready else Bool(false))
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io.deq.bits <> ram(deq_ptr)
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val ptr_diff = enq_ptr - deq_ptr
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if (pow2)
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io.count := Cat(maybe_full && ptr_match, ptr_diff).toUFix
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else
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io.count := Mux(ptr_match, Mux(maybe_full, UFix(entries), UFix(0)), Mux(deq_ptr > enq_ptr, UFix(entries) + ptr_diff, ptr_diff))
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}
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object Queue
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{
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def apply[T <: Data](enq: FIFOIO[T], entries: Int = 2, pipe: Boolean = false) = {
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val q = (new queue(entries, pipe)) { enq.bits.clone }
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q.io.enq.valid := enq.valid // not using <> so that override is allowed
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q.io.enq.bits := enq.bits
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enq.ready := q.io.enq.ready
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q.io.deq
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}
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}
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class pipereg[T <: Data]()(data: => T) extends Component
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{
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val io = new Bundle {
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val enq = new PipeIO()(data).flip
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val deq = new PipeIO()(data)
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}
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//val bits = Reg() { io.enq.bits.clone }
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//when (io.enq.valid) {
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// bits := io.enq.bits
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//}
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val reg = Reg() { io.enq.bits.clone }
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when (io.enq.valid) { reg := io.enq.bits }
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io.deq.valid := Reg(io.enq.valid, resetVal = Bool(false))
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io.deq.bits <> reg
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}
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object Pipe
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{
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def apply[T <: Data](enq: PipeIO[T], latency: Int = 1): PipeIO[T] = {
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val q = (new pipereg) { enq.bits.clone }
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q.io.enq <> enq
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q.io.deq
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if (latency > 1)
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Pipe(q.io.deq, latency-1)
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else
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q.io.deq
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}
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}
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