riscv/rocket-chip
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Ignore rocc interrupt line when no rocc is present

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This commit is contained in:
Andrew Waterman
2014-02-06 03:06:55 -08:00
parent e7a726fbac
commit eca8c99f44
1 changed files with 3 additions and 2 deletions
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5
rocket/src/main/scala/dpath_util.scala
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@@ -132,6 +132,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val r_irq_timer = Reg(init=Bool(false)) val r_irq_timer = Reg(init=Bool(false))
val r_irq_ipi = Reg(init=Bool(true)) val r_irq_ipi = Reg(init=Bool(true))
val irq_rocc = Bool(!conf.rocc.isEmpty) && io.rocc.interrupt
val cpu_req_valid = io.rw.cmd != CSR.N val cpu_req_valid = io.rw.cmd != CSR.N
val host_pcr_req_valid = Reg(Bool()) // don't reset val host_pcr_req_valid = Reg(Bool()) // don't reset
@@ -171,8 +172,8 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data) val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data)
io.status := reg_status io.status := reg_status
io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false), io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
Bool(false), io.rocc.interrupt, Bool(false), Bool(false)) Bool(false), irq_rocc, Bool(false), Bool(false))
io.fatc := wen && decoded_addr(CSRs.fatc) io.fatc := wen && decoded_addr(CSRs.fatc)
io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
io.ptbr := reg_ptbr io.ptbr := reg_ptbr