From eca8c99f44444c0053d1b251a6d6a3df2ea20468 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 6 Feb 2014 03:06:55 -0800 Subject: [PATCH] Ignore rocc interrupt line when no rocc is present --- rocket/src/main/scala/dpath_util.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 803d6908..3d1922b1 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -132,6 +132,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module val r_irq_timer = Reg(init=Bool(false)) val r_irq_ipi = Reg(init=Bool(true)) + val irq_rocc = Bool(!conf.rocc.isEmpty) && io.rocc.interrupt val cpu_req_valid = io.rw.cmd != CSR.N val host_pcr_req_valid = Reg(Bool()) // don't reset @@ -171,8 +172,8 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data) io.status := reg_status - io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false), - Bool(false), io.rocc.interrupt, Bool(false), Bool(false)) + io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false), + Bool(false), irq_rocc, Bool(false), Bool(false)) io.fatc := wen && decoded_addr(CSRs.fatc) io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt io.ptbr := reg_ptbr