riscv/rocket-chip
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Fix data array reset bug

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io.resp.valid could have been valid the cycle after reset, causing the
write mask in the acquire tracker to have an erroneous value after reset.
This caused the L1 I$ to be refilled with the wrong data.

This probably only affects programs loaded with +loadmem and so shouldn't
matter for the EOS24 silicon.  It should only affect the first L2 xact,
which, in practice, would be an HTIF write to load the program.
This commit is contained in:
Andrew Waterman 2015-06-11 15:28:23 -07:00
parent f3a838cedf
commit ea76800d1a
1 changed files with 3 additions and 4 deletions
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7
uncore/src/main/scala/cache.scala
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@ -329,10 +329,9 @@ class L2DataArray(delay: Int) extends L2HellaCacheModule {
reg_raddr := raddr reg_raddr := raddr
} }
io.resp.valid := ShiftRegister(io.read.fire(), delay+1) val r_req = Pipe(io.read.fire(), io.read.bits)
io.resp.bits.id := ShiftRegister(io.read.bits.id, delay+1) io.resp := Pipe(r_req.valid, r_req.bits, delay)
io.resp.bits.addr_beat := ShiftRegister(io.read.bits.addr_beat, delay+1) io.resp.bits.data := Pipe(r_req.valid, array(reg_raddr), delay).bits
io.resp.bits.data := ShiftRegister(array(reg_raddr), delay)
io.read.ready := !io.write.valid io.read.ready := !io.write.valid
io.write.ready := Bool(true) io.write.ready := Bool(true)
} }