From ea76800d1ae15e2f2fc1e388670f5808c38946dc Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 11 Jun 2015 15:28:23 -0700 Subject: [PATCH] Fix data array reset bug io.resp.valid could have been valid the cycle after reset, causing the write mask in the acquire tracker to have an erroneous value after reset. This caused the L1 I$ to be refilled with the wrong data. This probably only affects programs loaded with +loadmem and so shouldn't matter for the EOS24 silicon. It should only affect the first L2 xact, which, in practice, would be an HTIF write to load the program. --- uncore/src/main/scala/cache.scala | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala index 4c2b1a88..925d0648 100644 --- a/uncore/src/main/scala/cache.scala +++ b/uncore/src/main/scala/cache.scala @@ -329,10 +329,9 @@ class L2DataArray(delay: Int) extends L2HellaCacheModule { reg_raddr := raddr } - io.resp.valid := ShiftRegister(io.read.fire(), delay+1) - io.resp.bits.id := ShiftRegister(io.read.bits.id, delay+1) - io.resp.bits.addr_beat := ShiftRegister(io.read.bits.addr_beat, delay+1) - io.resp.bits.data := ShiftRegister(array(reg_raddr), delay) + val r_req = Pipe(io.read.fire(), io.read.bits) + io.resp := Pipe(r_req.valid, r_req.bits, delay) + io.resp.bits.data := Pipe(r_req.valid, array(reg_raddr), delay).bits io.read.ready := !io.write.valid io.write.ready := Bool(true) }