riscv/rocket-chip
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Merge branch 'master' into hwacha-port

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Stephen Twigg
2014-01-21 15:23:05 -08:00
parent ee0c4ca291 6f7ae01b1a
commit e7ee94bcc8
2 changed files with 4 additions and 4 deletions
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src/main/scala/RocketChip.scala
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@@ -251,7 +251,7 @@ class Top extends Module {
implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38)
val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val vic = ICacheConfig(128, 1)