From 25fdf9827f82a1931b4e1eabcfde6b118026549e Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 21 Nov 2013 14:45:59 -0800 Subject: [PATCH 1/9] push tests --- riscv-tests | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-tests b/riscv-tests index 532db85c..fdf5e6f9 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 532db85c68d3517ed46f2d9203a3e72db5c8dec3 +Subproject commit fdf5e6f97d53722d7ec44c4591f1ab740a092808 From 951226f4135aaca6457466723a96b3c11adb3465 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 21 Nov 2013 14:46:31 -0800 Subject: [PATCH 2/9] fix slli/slliw encoding bug --- riscv-tools | 2 +- rocket | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tools b/riscv-tools index 17a9427f..e5307451 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 17a9427f93b7319c5e27051bbd6d4d3b8026f70c +Subproject commit e5307451589e339c56e54e869bdb1d74c6cb8e90 diff --git a/rocket b/rocket index bad7213d..80c4fb65 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit bad7213d9dcb064fb1fe53395fdcd47092fb9e96 +Subproject commit 80c4fb65f40917b076576a30b574bdd4a0126251 From 9e6e5adeba78244281438c6b0972bec5b0f9916c Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 21 Nov 2013 14:55:57 -0800 Subject: [PATCH 3/9] push uncore --- uncore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore b/uncore index 9eadc3d8..ac4a5373 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 9eadc3d8c87507fbc8981d3ff9a7490ab8a35851 +Subproject commit ac4a5373c69c04a003bebe54fb7eca7387a43e4d From a43cf9d68896a6e05b772c4d8a6dcab21709f44b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 25 Nov 2013 04:44:55 -0800 Subject: [PATCH 4/9] Update to new privileged ISA --- chisel | 2 +- riscv-tests | 2 +- riscv-tools | 2 +- rocket | 2 +- src/main/scala/RocketChip.scala | 2 +- src/main/scala/fpga.scala | 2 +- uncore | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/chisel b/chisel index 4483d414..8dc0a8e6 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 4483d41471e4cb8e77b61f3f13255f4d59425d61 +Subproject commit 8dc0a8e6954bc4b40e5004c451bd12020c2ae0cb diff --git a/riscv-tests b/riscv-tests index fdf5e6f9..b374fd10 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit fdf5e6f97d53722d7ec44c4591f1ab740a092808 +Subproject commit b374fd10b2b36124bb6813211a7ec690e1fa8350 diff --git a/riscv-tools b/riscv-tools index e5307451..20ff67d5 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit e5307451589e339c56e54e869bdb1d74c6cb8e90 +Subproject commit 20ff67d56c3b505b99e531d48954c2c292a2fa99 diff --git a/rocket b/rocket index 80c4fb65..ba63ecb7 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 80c4fb65f40917b076576a30b574bdd4a0126251 +Subproject commit ba63ecb7cf3d2d2d871f35225ea89ba3141b8dae diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index b1df61c0..90cccf9c 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf val mem_backup = new ioMemSerialized(htif_width) val mem_backup_en = Bool(INPUT) } - val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) + val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 3aab9d29..e491caba 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput } - val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) + val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif diff --git a/uncore b/uncore index ac4a5373..2a21e843 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit ac4a5373c69c04a003bebe54fb7eca7387a43e4d +Subproject commit 2a21e8435a0b58ca588bfda0ab11b54e08efe3bd From ab6cd9c9e8903e1e7c130a5127587484e8af3907 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 9 Dec 2013 15:09:48 -0800 Subject: [PATCH 5/9] Update chisel, rocket --- chisel | 2 +- csrc/emulator.cc | 2 +- rocket | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/chisel b/chisel index 8dc0a8e6..22ab4efe 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 8dc0a8e6954bc4b40e5004c451bd12020c2ae0cb +Subproject commit 22ab4efe5878b0d6eb324b820ef8cea381698efd diff --git a/csrc/emulator.cc b/csrc/emulator.cc index 3765e161..587036b9 100644 --- a/csrc/emulator.cc +++ b/csrc/emulator.cc @@ -125,7 +125,7 @@ int main(int argc, char** argv) } if (log) - tile.print(stderr); + tile.print(stderr, stderr); if (vcd) tile.dump(vcdfile, trace_count); diff --git a/rocket b/rocket index ba63ecb7..6554ed32 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit ba63ecb7cf3d2d2d871f35225ea89ba3141b8dae +Subproject commit 6554ed321ceef75af96aeab6a4d8a2b9d90c0d1d From d99ee1f9c27b6b9decc0b6751d1108ee563a8e99 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 9 Dec 2013 20:31:58 -0800 Subject: [PATCH 6/9] Update hardfloat, fixing SFMA unit --- hardfloat | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardfloat b/hardfloat index def6363b..ac7ec37a 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit def6363b442dc1c8b386d9e9d3c19edad54313f3 +Subproject commit ac7ec37adf725caf9291d813e46826a9a7cab22c From dfc13236d1a140d7ccb9450a8bfe2876c3cb4ea1 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 16 Jan 2014 12:44:29 -0800 Subject: [PATCH 7/9] Linux works again! --- chisel | 2 +- csrc/emulator.cc | 6 +++--- riscv-tests | 2 +- riscv-tools | 2 +- rocket | 2 +- uncore | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/chisel b/chisel index 22ab4efe..ae1d1de8 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 22ab4efe5878b0d6eb324b820ef8cea381698efd +Subproject commit ae1d1de82188f0a1d79a4e8eb613743942a13eb3 diff --git a/csrc/emulator.cc b/csrc/emulator.cc index 587036b9..19d9fe92 100644 --- a/csrc/emulator.cc +++ b/csrc/emulator.cc @@ -94,7 +94,7 @@ int main(int argc, char** argv) tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready()); tile.Top__io_mem_resp_valid = LIT<1>(mm->resp_valid()); tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag()); - memcpy(&tile.Top__io_mem_resp_bits_data, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8); + memcpy(tile.Top__io_mem_resp_bits_data.values, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8); tile.clock_lo(LIT<1>(0)); @@ -105,7 +105,7 @@ int main(int argc, char** argv) tile.Top__io_mem_req_cmd_bits_tag.lo_word(), tile.Top__io_mem_req_data_valid.lo_word(), - &tile.Top__io_mem_req_data_bits_data.values[0], + tile.Top__io_mem_req_data_bits_data.values, tile.Top__io_mem_resp_ready.to_bool() ); @@ -120,7 +120,7 @@ int main(int argc, char** argv) tile.Top__io_host_in_bits = LIT<64>(htif_in_bits); if (tile.Top__io_host_out_valid.to_bool()) - htif->send(&tile.Top__io_host_out_bits.values[0], htif_bits/8); + htif->send(tile.Top__io_host_out_bits.values, htif_bits/8); tile.Top__io_host_out_ready = LIT<1>(1); } diff --git a/riscv-tests b/riscv-tests index b374fd10..d710b4ba 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit b374fd10b2b36124bb6813211a7ec690e1fa8350 +Subproject commit d710b4ba5d3405a338d133f77f5d19bd12a4e8b7 diff --git a/riscv-tools b/riscv-tools index 20ff67d5..fb38473b 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 20ff67d56c3b505b99e531d48954c2c292a2fa99 +Subproject commit fb38473be6f843cc492e03a0669ed60df7d05c5c diff --git a/rocket b/rocket index 6554ed32..2249bbfb 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 6554ed321ceef75af96aeab6a4d8a2b9d90c0d1d +Subproject commit 2249bbfbdebdd6f2a02c34793024332a08c9167d diff --git a/uncore b/uncore index 2a21e843..a5826575 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 2a21e8435a0b58ca588bfda0ab11b54e08efe3bd +Subproject commit a58265755fcb90aebe5377cb9b7343732fd14b9a From 6f028b2d524d6bb2d3e0dac7bf6c04d2df6cd3a5 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 17 Jan 2014 03:53:08 -0800 Subject: [PATCH 8/9] Increase BTB size; fix Rocket FPU bug --- rocket | 2 +- src/main/scala/RocketChip.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket b/rocket index 2249bbfb..029a205b 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 2249bbfbdebdd6f2a02c34793024332a08c9167d +Subproject commit 029a205b207f3350e68e85d9fa69fa0e79140ac6 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 90cccf9c..deb400f7 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -251,7 +251,7 @@ class Top extends Module { implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS) implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) - val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16) + val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38) val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) val rc = RocketConfiguration(tl, ic, dc, From 6f7ae01b1ab60ac8430936464793d7b3f3915518 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 17 Jan 2014 14:10:10 -0800 Subject: [PATCH 9/9] More FPU fixes --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index 029a205b..019406da 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 029a205b207f3350e68e85d9fa69fa0e79140ac6 +Subproject commit 019406dafae1d5e4c55a58b9a89cd7ce6a933aa6