diff --git a/csrc/emulator.cc b/csrc/emulator.cc
index 587036b9..19d9fe92 100644
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@@ -94,7 +94,7 @@ int main(int argc, char** argv)
     tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready());
     tile.Top__io_mem_resp_valid = LIT<1>(mm->resp_valid());
     tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag());
-    memcpy(&tile.Top__io_mem_resp_bits_data, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8);
+    memcpy(tile.Top__io_mem_resp_bits_data.values, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8);
 
     tile.clock_lo(LIT<1>(0));
 
@@ -105,7 +105,7 @@ int main(int argc, char** argv)
       tile.Top__io_mem_req_cmd_bits_tag.lo_word(),
 
       tile.Top__io_mem_req_data_valid.lo_word(),
-      &tile.Top__io_mem_req_data_bits_data.values[0],
+      tile.Top__io_mem_req_data_bits_data.values,
 
       tile.Top__io_mem_resp_ready.to_bool()
     );
@@ -120,7 +120,7 @@ int main(int argc, char** argv)
       tile.Top__io_host_in_bits = LIT<64>(htif_in_bits);
 
       if (tile.Top__io_host_out_valid.to_bool())
-        htif->send(&tile.Top__io_host_out_bits.values[0], htif_bits/8);
+        htif->send(tile.Top__io_host_out_bits.values, htif_bits/8);
       tile.Top__io_host_out_ready = LIT<1>(1);
     }
 
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 083220d8..ab797386 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -251,7 +251,7 @@ class Top extends Module {
   implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
   implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
 
-  val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
+  val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38)
   val dc = DCacheConfig(128, 4, ntlb = 8, 
                         nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
   val vic = ICacheConfig(128, 1)