From e2185d40f6c239a3ba8752fecefbe8bde0e86408 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Sun, 6 Mar 2016 16:32:59 -0800 Subject: [PATCH] Avoid right-shift by larger that the bit width FIRRTL bails out on this. There's an outstanding bug, this is just a workaround. See https://github.com/ucb-bar/firrtl/issues/69 --- uncore/src/main/scala/tilelink.scala | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala index b8f1512c..c4850c62 100644 --- a/uncore/src/main/scala/tilelink.scala +++ b/uncore/src/main/scala/tilelink.scala @@ -1110,8 +1110,15 @@ abstract class TileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) exte trait AppendsArbiterId extends TileLinkArbiterLike { def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) = Cat(in.client_xact_id, UInt(id, log2Up(arbN))) - def managerSourcedClientXactId(in: ManagerSourcedWithId) = - in.client_xact_id >> log2Up(arbN) + def managerSourcedClientXactId(in: ManagerSourcedWithId) = { + /* This shouldn't be necessary, but Chisel3 doesn't emit correct Verilog + * when right shifting by too many bits. See + * https://github.com/ucb-bar/firrtl/issues/69 */ + if (in.client_xact_id.getWidth > log2Up(arbN)) + in.client_xact_id >> log2Up(arbN) + else + UInt(0) + } def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0).toUInt }