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tilelink2: use consistent in/out ports for TLSimpleFactories

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Wesley W. Terpstra 2016-08-30 10:40:54 -07:00
parent 1a87eef3e2
commit dd27a60daa
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/tilelink2/RegisterRouter.scala
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@ -64,7 +64,7 @@ abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatB
val node = TLRegisterNode(address, concurrency, beatBytes) val node = TLRegisterNode(address, concurrency, beatBytes)
} }
class TLRegBundle[P](val params: P, val tl_in: Vec[TLBundle]) extends Bundle class TLRegBundle[P](val params: P, val in: Vec[TLBundle]) extends Bundle
class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, factory: TLRegFactory) class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, factory: TLRegFactory)
extends TLModule(factory) with HasRegMap extends TLModule(factory) with HasRegMap