diff --git a/uncore/src/main/scala/tilelink2/RegisterRouter.scala b/uncore/src/main/scala/tilelink2/RegisterRouter.scala
index 35ff80d5..890e4a0b 100644
--- a/uncore/src/main/scala/tilelink2/RegisterRouter.scala
+++ b/uncore/src/main/scala/tilelink2/RegisterRouter.scala
@@ -64,7 +64,7 @@ abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatB
   val node = TLRegisterNode(address, concurrency, beatBytes)
 }
 
-class TLRegBundle[P](val params: P, val tl_in: Vec[TLBundle]) extends Bundle
+class TLRegBundle[P](val params: P, val in: Vec[TLBundle]) extends Bundle
 
 class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, factory: TLRegFactory)
   extends TLModule(factory) with HasRegMap